fmcadc1: sdc updates
parent
c0dd80ccee
commit
543e08b67a
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@ -6,5 +6,8 @@ create_clock -period "8.000 ns" -name eth_rx_clk_125mhz [get_ports {eth_rx
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derive_pll_clocks
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derive_pll_clocks
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derive_clock_uncertainty
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derive_clock_uncertainty
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set_clock_groups -exclusive \
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-group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] \
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-group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] \
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-group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] \
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@ -291,11 +291,11 @@ module system_top (
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.sys_spi_MOSI (spi_mosi),
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.sys_spi_MOSI (spi_mosi),
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.sys_spi_SCLK (spi_clk),
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.sys_spi_SCLK (spi_clk),
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.sys_spi_SS_n (spi_csn),
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.sys_spi_SS_n (spi_csn),
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.sys_xcvr_reset_reset (gpio_jesd_o[15]),
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.sys_xcvr_reset_reset (gpio_jesd_o[15]),
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.sys_xcvr_rstcntrl_rx_ready_rx_ready (rx_ready),
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.sys_xcvr_rstcntrl_rx_ready_rx_ready (rx_ready),
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.sys_xcvr_rx_ref_clk_clk (ref_clk),
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.sys_xcvr_rx_ref_clk_clk (ref_clk),
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.sys_xcvr_rx_sync_n_export (rx_sync),
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.sys_xcvr_rx_sync_n_export (rx_sync),
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.sys_xcvr_rx_sysref_export (rx_sysref),
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.sys_xcvr_rx_sysref_export (rx_sysref),
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.sys_xcvr_rxd_rx_serial_data (rx_data));
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.sys_xcvr_rxd_rx_serial_data (rx_data));
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endmodule
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endmodule
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