diff --git a/projects/fmcjesdadc1/a5gt/system_constr.sdc b/projects/fmcjesdadc1/a5gt/system_constr.sdc
index efa554e74..5af36a64f 100644
--- a/projects/fmcjesdadc1/a5gt/system_constr.sdc
+++ b/projects/fmcjesdadc1/a5gt/system_constr.sdc
@@ -6,5 +6,8 @@ create_clock -period "8.000 ns"   -name eth_rx_clk_125mhz     [get_ports {eth_rx
 derive_pll_clocks
 derive_clock_uncertainty
 
-
+set_clock_groups -exclusive \
+  -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] \
+  -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] \
+  -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] \
 
diff --git a/projects/fmcjesdadc1/a5gt/system_top.v b/projects/fmcjesdadc1/a5gt/system_top.v
index 8c7934b55..ccdba6e55 100644
--- a/projects/fmcjesdadc1/a5gt/system_top.v
+++ b/projects/fmcjesdadc1/a5gt/system_top.v
@@ -291,11 +291,11 @@ module system_top (
     .sys_spi_MOSI (spi_mosi),
     .sys_spi_SCLK (spi_clk),
     .sys_spi_SS_n (spi_csn),
-		.sys_xcvr_reset_reset (gpio_jesd_o[15]),
-		.sys_xcvr_rstcntrl_rx_ready_rx_ready (rx_ready),
-		.sys_xcvr_rx_ref_clk_clk (ref_clk),
-		.sys_xcvr_rx_sync_n_export (rx_sync),
-		.sys_xcvr_rx_sysref_export (rx_sysref),
+    .sys_xcvr_reset_reset (gpio_jesd_o[15]),
+    .sys_xcvr_rstcntrl_rx_ready_rx_ready (rx_ready),
+    .sys_xcvr_rx_ref_clk_clk (ref_clk),
+    .sys_xcvr_rx_sync_n_export (rx_sync),
+    .sys_xcvr_rx_sysref_export (rx_sysref),
 		.sys_xcvr_rxd_rx_serial_data (rx_data));
 
 endmodule