ad7134_fmc: Initial commit
Istvan Csomortani
István Csomortáni
parent
cd94f2f249
commit
53fa482837
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@ -9,6 +9,7 @@
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all:
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-$(MAKE) -C ad5766_sdz all
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-$(MAKE) -C ad6676evb all
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-$(MAKE) -C ad7134_fmc all
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-$(MAKE) -C ad738x_fmc all
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-$(MAKE) -C ad7616_sdz all
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-$(MAKE) -C ad77681evb all
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@ -47,6 +48,7 @@ all:
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clean:
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$(MAKE) -C ad5766_sdz clean
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$(MAKE) -C ad6676evb clean
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$(MAKE) -C ad7134_fmc clean
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$(MAKE) -C ad738x_fmc clean
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$(MAKE) -C ad7616_sdz clean
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$(MAKE) -C ad77681evb clean
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@ -85,6 +87,7 @@ clean:
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clean-all:
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$(MAKE) -C ad5766_sdz clean-all
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$(MAKE) -C ad6676evb clean-all
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$(MAKE) -C ad7134_fmc clean-all
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$(MAKE) -C ad738x_fmc clean-all
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$(MAKE) -C ad7616_sdz clean-all
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$(MAKE) -C ad77681evb clean-all
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@ -0,0 +1,21 @@
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####################################################################################
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####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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.PHONY: all clean clean-all
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all:
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-$(MAKE) -C zed all
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clean:
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$(MAKE) -C zed clean
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clean-all:
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$(MAKE) -C zed clean-all
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####################################################################################
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####################################################################################
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@ -0,0 +1,128 @@
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad713x_di
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create_bd_port -dir I ad713x_odr
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create_bd_port -dir O ad713x_sdpclk
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# create a SPI Engine architecture for the parallel data interface of AD713x
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# this design supports AD7132/AD7134/AD7136
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create_bd_cell -type hier dual_ad7134
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current_bd_instance /dual_ad7134
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create_bd_pin -dir I -type clk clk
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create_bd_pin -dir I -type rst resetn
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create_bd_pin -dir I odr
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create_bd_pin -dir O irq
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
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ad_ip_instance spi_engine_execution execution
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ad_ip_parameter execution CONFIG.DATA_WIDTH $adc_resolution
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ad_ip_parameter execution CONFIG.NUM_OF_CS 1
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ad_ip_parameter execution CONFIG.NUM_OF_SDI $adc_num_of_channels
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ad_ip_instance axi_spi_engine axi
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ad_ip_parameter axi CONFIG.DATA_WIDTH $adc_resolution
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ad_ip_parameter axi CONFIG.NUM_OF_SDI $adc_num_of_channels
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ad_ip_parameter axi CONFIG.NUM_OFFLOAD 1
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ad_ip_instance spi_engine_offload offload
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ad_ip_parameter offload CONFIG.DATA_WIDTH $adc_resolution
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ad_ip_parameter offload CONFIG.NUM_OF_SDI $adc_num_of_channels
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ad_ip_parameter offload CONFIG.ASYNC_TRIG 1
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ad_ip_instance spi_engine_interconnect interconnect
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ad_ip_parameter interconnect CONFIG.DATA_WIDTH $adc_resolution
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ad_ip_parameter interconnect CONFIG.NUM_OF_SDI $adc_num_of_channels
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if {$adc_resolution == 24} {
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ad_ip_instance util_axis_upscale axis_upscaler
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ad_ip_parameter axis_upscaler CONFIG.NUM_OF_CHANNELS $adc_num_of_channels
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ad_ip_parameter axis_upscaler CONFIG.DATA_WIDTH 24
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ad_ip_parameter axis_upscaler CONFIG.UDATA_WIDTH 32
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ad_connect axis_upscaler/dfmt_enable GND
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ad_connect axis_upscaler/dfmt_type GND
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ad_connect axis_upscaler/dfmt_se GND
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}
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ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
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ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
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ad_connect axi/spi_engine_ctrl interconnect/s1_ctrl
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ad_connect interconnect/m_ctrl execution/ctrl
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if {$adc_resolution == 24} {
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ad_connect offload/offload_sdi axis_upscaler/s_axis
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ad_connect axis_upscaler/m_axis M_AXIS_SAMPLE
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ad_connect clk axis_upscaler/clk
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ad_connect axi/spi_resetn axis_upscaler/resetn
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} else {
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ad_connect offload/offload_sdi M_AXIS_SAMPLE
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}
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ad_connect execution/spi m_spi
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ad_connect clk offload/spi_clk
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ad_connect clk offload/ctrl_clk
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ad_connect clk execution/clk
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ad_connect clk axi/s_axi_aclk
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ad_connect clk axi/spi_clk
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ad_connect clk interconnect/clk
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ad_connect axi/spi_resetn offload/spi_resetn
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ad_connect axi/spi_resetn execution/resetn
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ad_connect axi/spi_resetn interconnect/resetn
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ad_connect odr offload/trigger
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ad_connect resetn axi/s_axi_aresetn
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ad_connect irq axi/irq
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current_bd_instance /
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# dma to receive data stream
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ad_ip_instance axi_dmac axi_ad7134_dma
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ad_ip_parameter axi_ad7134_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad7134_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad7134_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad7134_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_ad7134_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad7134_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_ad7134_dma CONFIG.DMA_2D_TRANSFER 0
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if {$adc_resolution == 24} {
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ad_ip_parameter axi_ad7134_dma CONFIG.DMA_DATA_WIDTH_SRC [expr 32 * $adc_num_of_channels]
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} else {
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ad_ip_parameter axi_ad7134_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $adc_resolution * $adc_num_of_channels]
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}
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ad_ip_parameter axi_ad7134_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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# sdpclk clock generator - default clk0_out is 50 MHz
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ad_ip_instance axi_clkgen axi_sdp_clkgen
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ad_ip_parameter axi_sdp_clkgen CONFIG.CLKIN_PERIOD 10
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ad_ip_parameter axi_sdp_clkgen CONFIG.VCO_MUL 12
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ad_ip_parameter axi_sdp_clkgen CONFIG.VCO_DIV 2
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ad_ip_parameter axi_sdp_clkgen CONFIG.CLK0_DIV 12
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ad_connect sys_cpu_clk dual_ad7134/clk
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ad_connect sys_cpu_clk axi_ad7134_dma/s_axis_aclk
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ad_connect sys_cpu_clk axi_sdp_clkgen/clk
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ad_connect sys_cpu_resetn dual_ad7134/resetn
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ad_connect sys_cpu_resetn axi_ad7134_dma/m_dest_axi_aresetn
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ad_connect dual_ad7134/m_spi ad713x_di
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ad_connect dual_ad7134/odr ad713x_odr
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ad_connect axi_ad7134_dma/s_axis dual_ad7134/M_AXIS_SAMPLE
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ad_connect ad713x_sdpclk axi_sdp_clkgen/clk_0
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ad_cpu_interconnect 0x44a00000 dual_ad7134/axi
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ad_cpu_interconnect 0x44a30000 axi_ad7134_dma
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ad_cpu_interconnect 0x44a40000 axi_sdp_clkgen
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ad_cpu_interrupt "ps-13" "mb-13" axi_ad7134_dma/irq
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ad_cpu_interrupt "ps-12" "mb-12" dual_ad7134/irq
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ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_cpu_clk axi_ad7134_dma/m_dest_axi
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@ -0,0 +1,90 @@
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####################################################################################
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####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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M_DEPS += system_top.v
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M_DEPS += system_project.tcl
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M_DEPS += system_constr.xdc
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M_DEPS += system_bd.tcl
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M_DEPS += ../common/ad7134_bd.tcl
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M_DEPS += ../../scripts/adi_project.tcl
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M_DEPS += ../../scripts/adi_env.tcl
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M_DEPS += ../../scripts/adi_board.tcl
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M_DEPS += ../../common/zed/zed_system_constr.xdc
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M_DEPS += ../../common/zed/zed_system_bd.tcl
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M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
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M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
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M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
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M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
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M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
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M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
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M_DEPS += ../../../library/spi_engine/axi_spi_engine/axi_spi_engine.xpr
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M_DEPS += ../../../library/spi_engine/spi_engine_execution/spi_engine_execution.xpr
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M_DEPS += ../../../library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr
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M_DEPS += ../../../library/spi_engine/spi_engine_offload/spi_engine_offload.xpr
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M_DEPS += ../../../library/util_axis_upscale/util_axis_upscale.xpr
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M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr
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M_VIVADO := vivado -mode batch -source
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M_FLIST := *.cache
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M_FLIST += *.data
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M_FLIST += *.xpr
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M_FLIST += *.log
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M_FLIST += *.jou
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M_FLIST += xgui
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M_FLIST += *.runs
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M_FLIST += *.srcs
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M_FLIST += *.sdk
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M_FLIST += *.hw
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M_FLIST += *.sim
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M_FLIST += .Xil
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M_FLIST += *.ip_user_files
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.PHONY: all lib clean clean-all
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all: lib ad7134_fmc_zed.sdk/system_top.hdf
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clean:
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rm -rf $(M_FLIST)
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clean-all:clean
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$(MAKE) -C ../../../library/axi_clkgen clean
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$(MAKE) -C ../../../library/axi_dmac clean
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$(MAKE) -C ../../../library/axi_hdmi_tx clean
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$(MAKE) -C ../../../library/axi_i2s_adi clean
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$(MAKE) -C ../../../library/axi_spdif_tx clean
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$(MAKE) -C ../../../library/spi_engine/axi_spi_engine clean
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$(MAKE) -C ../../../library/spi_engine/spi_engine_execution clean
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$(MAKE) -C ../../../library/spi_engine/spi_engine_interconnect clean
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$(MAKE) -C ../../../library/spi_engine/spi_engine_offload clean
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$(MAKE) -C ../../../library/util_axis_upscale clean
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$(MAKE) -C ../../../library/util_i2c_mixer clean
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ad7134_fmc_zed.sdk/system_top.hdf: $(M_DEPS)
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-rm -rf $(M_FLIST)
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$(M_VIVADO) system_project.tcl >> ad7134_fmc_zed_vivado.log 2>&1
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lib:
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$(MAKE) -C ../../../library/axi_clkgen
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$(MAKE) -C ../../../library/axi_dmac
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$(MAKE) -C ../../../library/axi_hdmi_tx
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$(MAKE) -C ../../../library/axi_i2s_adi
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$(MAKE) -C ../../../library/axi_spdif_tx
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$(MAKE) -C ../../../library/spi_engine/axi_spi_engine
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$(MAKE) -C ../../../library/spi_engine/spi_engine_execution
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$(MAKE) -C ../../../library/spi_engine/spi_engine_interconnect
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$(MAKE) -C ../../../library/spi_engine/spi_engine_offload
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$(MAKE) -C ../../../library/util_axis_upscale
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$(MAKE) -C ../../../library/util_i2c_mixer
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####################################################################################
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####################################################################################
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@ -0,0 +1,13 @@
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
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# specify ADC resolution -- the design supports 16/24/32 bit resolutions
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set adc_resolution 24
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# ADC number of channels
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set adc_num_of_channels 8
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source ../common/ad7134_bd.tcl
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@ -0,0 +1,47 @@
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# ad713x SPI configuration interface
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set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad713x_spi_sdi] ; ## FMC_LPC_LA03_P
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set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports ad713x_spi_sdo] ; ## FMC_LPC_LA04_N
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set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad713x_spi_sclk] ; ## FMC_LPC_LA01_CC_P
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set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports ad713x_spi_cs[0]] ; ## FMC_LPC_LA05_P
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set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports ad713x_spi_cs[1]] ; ## FMC_LPC_LA05_N
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# ad713x data interface
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set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad713x_dclk] ; ## FMC_LPC_CLK0_M2C_P
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set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad713x_din[0]] ; ## FMC_LPC_LA00_CC_N
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set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports ad713x_din[1]] ; ## FMC_LPC_LA08_P
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set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad713x_din[2]] ; ## FMC_LPC_LA02_P
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set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad713x_din[3]] ; ## FMC_LPC_LA02_N
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set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports ad713x_din[4]] ; ## FMC_LPC_LA06_N
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set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports ad713x_din[5]] ; ## FMC_LPC_LA08_N
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set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports ad713x_din[6]] ; ## FMC_LPC_LA09_P
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set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports ad713x_din[7]] ; ## FMC_LPC_LA09_N
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set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports ad713x_odr] ; ## FMC_LPC_LA00_CC_P
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# ad713x GPIO lines
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set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports ad713x_resetn[0]] ; ## FMC_LPC_LA16_P
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set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports ad713x_resetn[1]] ; ## FMC_LPC_LA16_N
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set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports ad713x_pdn[0]] ; ## FMC_LPC_LA07_P
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set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports ad713x_pdn[1]] ; ## FMC_LPC_LA07_N
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set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad713x_mode[0]] ; ## FMC_LPC_LA04_P
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set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports ad713x_mode[1]] ; ## FMC_LPC_LA03_N
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set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports ad713x_gpio[0]] ; ## FMC_LPC_LA10_P
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set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports ad713x_gpio[1]] ; ## FMC_LPC_LA10_N
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set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports ad713x_gpio[2]] ; ## FMC_LPC_LA11_P
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set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports ad713x_gpio[3]] ; ## FMC_LPC_LA11_N
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set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports ad713x_gpio[4]] ; ## FMC_LPC_LA12_P
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set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports ad713x_gpio[5]] ; ## FMC_LPC_LA12_N
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set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports ad713x_gpio[6]] ; ## FMC_LPC_LA13_P
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set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports ad713x_gpio[7]] ; ## FMC_LPC_LA13_N
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set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25} [get_ports ad713x_dclkio[0]] ; ## FMC_LPC_LA14_P
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set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports ad713x_dclkio[1]] ; ## FMC_LPC_LA15_P
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set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports ad713x_pinbspi] ; ## FMC_LPC_LA06_P
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set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS25} [get_ports ad713x_dclkmode] ; ## FMC_LPC_LA14_N
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# ad713x reference clock (not used by default)
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set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad713x_sdpclk] ; ## FMC_LPC_LA01_CC_N
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@ -0,0 +1,15 @@
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project_xilinx ad7134_fmc_zed
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adi_project_files ad7134_fmc_zed [list \
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"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
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"system_top.v" \
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"system_constr.xdc" \
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"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
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adi_project_run ad7134_fmc_zed
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@ -0,0 +1,249 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsabilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top (
|
||||
|
||||
inout [14:0] ddr_addr,
|
||||
inout [ 2:0] ddr_ba,
|
||||
inout ddr_cas_n,
|
||||
inout ddr_ck_n,
|
||||
inout ddr_ck_p,
|
||||
inout ddr_cke,
|
||||
inout ddr_cs_n,
|
||||
inout [ 3:0] ddr_dm,
|
||||
inout [31:0] ddr_dq,
|
||||
inout [ 3:0] ddr_dqs_n,
|
||||
inout [ 3:0] ddr_dqs_p,
|
||||
inout ddr_odt,
|
||||
inout ddr_ras_n,
|
||||
inout ddr_reset_n,
|
||||
inout ddr_we_n,
|
||||
|
||||
inout fixed_io_ddr_vrn,
|
||||
inout fixed_io_ddr_vrp,
|
||||
inout [53:0] fixed_io_mio,
|
||||
inout fixed_io_ps_clk,
|
||||
inout fixed_io_ps_porb,
|
||||
inout fixed_io_ps_srstb,
|
||||
|
||||
inout [31:0] gpio_bd,
|
||||
|
||||
output hdmi_out_clk,
|
||||
output hdmi_vsync,
|
||||
output hdmi_hsync,
|
||||
output hdmi_data_e,
|
||||
output [15:0] hdmi_data,
|
||||
|
||||
output spdif,
|
||||
|
||||
output i2s_mclk,
|
||||
output i2s_bclk,
|
||||
output i2s_lrclk,
|
||||
output i2s_sdata_out,
|
||||
input i2s_sdata_in,
|
||||
|
||||
|
||||
inout iic_scl,
|
||||
inout iic_sda,
|
||||
inout [ 1:0] iic_mux_scl,
|
||||
inout [ 1:0] iic_mux_sda,
|
||||
|
||||
input otg_vbusoc,
|
||||
|
||||
// ad713x SPI configuration interface
|
||||
|
||||
input ad713x_spi_sdi,
|
||||
output ad713x_spi_sdo,
|
||||
output ad713x_spi_sclk,
|
||||
output [ 1:0] ad713x_spi_cs,
|
||||
|
||||
// ad713x data interface
|
||||
|
||||
output ad713x_dclk,
|
||||
input [ 7:0] ad713x_din,
|
||||
input ad713x_odr,
|
||||
|
||||
// ad713x GPIO lines
|
||||
|
||||
inout [ 1:0] ad713x_resetn,
|
||||
inout [ 1:0] ad713x_pdn,
|
||||
inout [ 1:0] ad713x_mode,
|
||||
inout [ 7:0] ad713x_gpio,
|
||||
inout [ 1:0] ad713x_dclkio,
|
||||
inout ad713x_pinbspi,
|
||||
inout ad713x_dclkmode,
|
||||
|
||||
// ad713x reference clock (not used by default)
|
||||
|
||||
output ad713x_sdpclk);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [63:0] gpio_i;
|
||||
wire [63:0] gpio_o;
|
||||
wire [63:0] gpio_t;
|
||||
wire [ 1:0] iic_mux_scl_i_s;
|
||||
wire [ 1:0] iic_mux_scl_o_s;
|
||||
wire iic_mux_scl_t_s;
|
||||
wire [ 1:0] iic_mux_sda_i_s;
|
||||
wire [ 1:0] iic_mux_sda_o_s;
|
||||
wire iic_mux_sda_t_s;
|
||||
|
||||
// instantiations
|
||||
|
||||
assign gpio_i[63:50] = gpio_o[63:50];
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(18)
|
||||
) i_iobuf_ad713x_gpio (
|
||||
.dio_t(gpio_t[49:32]),
|
||||
.dio_i(gpio_o[49:32]),
|
||||
.dio_o(gpio_i[49:32]),
|
||||
.dio_p({ad713x_dclkmode, // [49]
|
||||
ad713x_pinbspi, // [48]
|
||||
ad713x_dclkio, // [47:46]
|
||||
ad713x_gpio, // [45:38]
|
||||
ad713x_mode, // [37:36]
|
||||
ad713x_pdn, // [35:34]
|
||||
ad713x_resetn})); // [33:32]
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(32)
|
||||
) i_iobuf (
|
||||
.dio_t(gpio_t[31:0]),
|
||||
.dio_i(gpio_o[31:0]),
|
||||
.dio_o(gpio_i[31:0]),
|
||||
.dio_p(gpio_bd));
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(2)
|
||||
) i_iic_mux_scl (
|
||||
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
|
||||
.dio_i(iic_mux_scl_o_s),
|
||||
.dio_o(iic_mux_scl_i_s),
|
||||
.dio_p(iic_mux_scl));
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(2)
|
||||
) i_iic_mux_sda (
|
||||
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
|
||||
.dio_i(iic_mux_sda_o_s),
|
||||
.dio_o(iic_mux_sda_i_s),
|
||||
.dio_p(iic_mux_sda));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
.ddr_ck_n (ddr_ck_n),
|
||||
.ddr_ck_p (ddr_ck_p),
|
||||
.ddr_cke (ddr_cke),
|
||||
.ddr_cs_n (ddr_cs_n),
|
||||
.ddr_dm (ddr_dm),
|
||||
.ddr_dq (ddr_dq),
|
||||
.ddr_dqs_n (ddr_dqs_n),
|
||||
.ddr_dqs_p (ddr_dqs_p),
|
||||
.ddr_odt (ddr_odt),
|
||||
.ddr_ras_n (ddr_ras_n),
|
||||
.ddr_reset_n (ddr_reset_n),
|
||||
.ddr_we_n (ddr_we_n),
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
.hdmi_out_clk (hdmi_out_clk),
|
||||
.hdmi_vsync (hdmi_vsync),
|
||||
.i2s_bclk (i2s_bclk),
|
||||
.i2s_lrclk (i2s_lrclk),
|
||||
.i2s_mclk (i2s_mclk),
|
||||
.i2s_sdata_in (i2s_sdata_in),
|
||||
.i2s_sdata_out (i2s_sdata_out),
|
||||
.iic_fmc_scl_io (iic_scl),
|
||||
.iic_fmc_sda_io (iic_sda),
|
||||
.iic_mux_scl_i (iic_mux_scl_i_s),
|
||||
.iic_mux_scl_o (iic_mux_scl_o_s),
|
||||
.iic_mux_scl_t (iic_mux_scl_t_s),
|
||||
.iic_mux_sda_i (iic_mux_sda_i_s),
|
||||
.iic_mux_sda_o (iic_mux_sda_o_s),
|
||||
.iic_mux_sda_t (iic_mux_sda_t_s),
|
||||
.ps_intr_00 (1'b0),
|
||||
.ps_intr_01 (1'b0),
|
||||
.ps_intr_02 (1'b0),
|
||||
.ps_intr_03 (1'b0),
|
||||
.ps_intr_04 (1'b0),
|
||||
.ps_intr_05 (1'b0),
|
||||
.ps_intr_06 (1'b0),
|
||||
.ps_intr_07 (1'b0),
|
||||
.ps_intr_08 (1'b0),
|
||||
.ps_intr_09 (1'b0),
|
||||
.ps_intr_10 (1'b0),
|
||||
.spi0_clk_i (ad713x_spi_sclk),
|
||||
.spi0_clk_o (ad713x_spi_sclk),
|
||||
.spi0_csn_0_o (ad713x_spi_cs[0]),
|
||||
.spi0_csn_1_o (ad713x_spi_cs[1]),
|
||||
.spi0_csn_i (1'b1),
|
||||
.spi0_sdi_i (ad713x_spi_sdi),
|
||||
.spi0_sdo_i (ad713x_spi_sdo),
|
||||
.spi0_sdo_o (ad713x_spi_sdo),
|
||||
.ad713x_di_sdo (),
|
||||
.ad713x_di_sdo_t (),
|
||||
.ad713x_di_sdi (ad713x_din[0]),
|
||||
.ad713x_di_sdi_1 (ad713x_din[1]),
|
||||
.ad713x_di_sdi_2 (ad713x_din[2]),
|
||||
.ad713x_di_sdi_3 (ad713x_din[3]),
|
||||
.ad713x_di_sdi_4 (ad713x_din[4]),
|
||||
.ad713x_di_sdi_5 (ad713x_din[5]),
|
||||
.ad713x_di_sdi_6 (ad713x_din[6]),
|
||||
.ad713x_di_sdi_7 (ad713x_din[7]),
|
||||
.ad713x_di_cs (),
|
||||
.ad713x_di_sclk (ad713x_dclk),
|
||||
.ad713x_odr (ad713x_odr),
|
||||
.ad713x_sdpclk (ad713x_sdpclk),
|
||||
.otg_vbusoc (otg_vbusoc),
|
||||
.spdif (spdif));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue