From 52df3c4937e178d43c7b2a3af98247601b1cb166 Mon Sep 17 00:00:00 2001 From: sergiu arpadi Date: Tue, 26 Oct 2021 15:42:00 +0300 Subject: [PATCH] ad463x_data_capture: Remove tb --- .../tb/ad463x_data_capture_tb | 10 - .../tb/ad463x_data_capture_tb.sv | 268 ------------------ 2 files changed, 278 deletions(-) delete mode 100755 library/ad463x_data_capture/tb/ad463x_data_capture_tb delete mode 100644 library/ad463x_data_capture/tb/ad463x_data_capture_tb.sv diff --git a/library/ad463x_data_capture/tb/ad463x_data_capture_tb b/library/ad463x_data_capture/tb/ad463x_data_capture_tb deleted file mode 100755 index 008cc1c8a..000000000 --- a/library/ad463x_data_capture/tb/ad463x_data_capture_tb +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/bash - -SOURCE="../ad463x_data_capture.v" -SOURCE+=" ad463x_data_capture_tb.sv" - -TOP="ad463x_data_capture_tb" - -cd `dirname $0` -source "../../common/tb/run_tb.sh" - diff --git a/library/ad463x_data_capture/tb/ad463x_data_capture_tb.sv b/library/ad463x_data_capture/tb/ad463x_data_capture_tb.sv deleted file mode 100644 index 3d9f09c67..000000000 --- a/library/ad463x_data_capture/tb/ad463x_data_capture_tb.sv +++ /dev/null @@ -1,268 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module ad463x_data_capture_tb (); - - parameter VCD_FILE = {`__FILE__,"cd"}; - - // set to one to increase verbosity - localparam DEBUG = 1; - localparam PASSED = 1; - localparam FAILED = 0; - - localparam DDR_EN = 0; - localparam NUM_OF_LANES = 1; - localparam TRANSFER_CYCLE = 120; - localparam TRANSFER_PERIOD = 40; - - reg clk = 1'b0; - reg [NUM_OF_LANES-1:0] data_in = {NUM_OF_LANES{1'b0}}; - reg m_axis_ready = 1'b1; - reg csn_clk = 1; - - wire csn; - wire echo_sclk; - wire m_axis_valid; - wire [(NUM_OF_LANES *32)-1:0] m_axis_data; - - //--------------------------------------------------------------------------- - // test bench regs and wires - //--------------------------------------------------------------------------- - - reg echo_sclk_int = 0; - integer csn_counter = 0; - - //--------------------------------------------------------------------------- - // VCD dump - //--------------------------------------------------------------------------- - - initial begin - $dumpfile (VCD_FILE); - $dumpvars; - end - - //--------------------------------------------------------------------------- - // clock generation - //--------------------------------------------------------------------------- - - always #5 clk = ~clk; - always #10 echo_sclk_int = ~echo_sclk_int; - - //--------------------------------------------------------------------------- - // chis select generation - //--------------------------------------------------------------------------- - - always @(negedge clk) begin - if (csn_counter == TRANSFER_CYCLE-1) - csn_counter = 0; - else - csn_counter++; - end - assign csn = (csn_counter < TRANSFER_CYCLE - TRANSFER_PERIOD) ? 1'b1 : 1'b0; - - assign echo_sclk = ~csn & echo_sclk_int; - - // CSN for DUT must be synchronous to clk - always @(posedge clk) begin - csn_clk <= csn; - end - //--------------------------------------------------------------------------- - // device BFM - MISO (SDO) generation - //--------------------------------------------------------------------------- - - reg csn_d = 0; - always @(posedge clk) begin - csn_d <= csn; - end - - reg [19:0] data_serial[NUM_OF_LANES-1:0]; - - // SDR - initial begin - while (1) begin - @(posedge echo_sclk or negedge csn); - if (csn_d) begin - for (int i=0; iend_of_sim; - #0 - print_status(tb_status); - - $finish; - end - - //-------------------------------------------------------------------------- - // Helper functions - //-------------------------------------------------------------------------- - - function print_queue(string queue_name, bit [31:0] queue[$]); - begin - $display("======================================"); - $display("Printing %s...", queue_name); - for(int i=0; i