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axi_ad9963: Updates for ad_dds phase acc wrapper

main
AndreiGrozav 2018-06-06 13:01:53 +03:00 committed by AndreiGrozav
parent 92dbd75414
commit 528460371c
5 changed files with 40 additions and 50 deletions
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3
library/axi_ad9963/Makefile
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@ -8,7 +8,10 @@ LIBRARY_NAME := axi_ad9963
GENERIC_DEPS += ../common/ad_datafmt.v
GENERIC_DEPS += ../common/ad_dds.v
GENERIC_DEPS += ../common/ad_dds_1.v
GENERIC_DEPS += ../common/ad_dds_2.v
GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v
GENERIC_DEPS += ../common/ad_dds_sine.v
GENERIC_DEPS += ../common/ad_dds_sine_cordic.v
GENERIC_DEPS += ../common/ad_iqcor.v
GENERIC_DEPS += ../common/ad_pnmon.v
GENERIC_DEPS += ../common/ad_rst.v

8
library/axi_ad9963/axi_ad9963.v
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@ -45,7 +45,8 @@ module axi_ad9963 #(
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter IODELAY_ENABLE = 0,
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_DW = 14,
parameter DAC_DDS_CORDIC_PHASE_DW = 13,
parameter DAC_DATAPATH_DISABLE = 0,
parameter ADC_USERPORTS_DISABLE = 0,
parameter ADC_DATAFORMAT_DISABLE = 0,
@ -250,8 +251,9 @@ module axi_ad9963 #(
axi_ad9963_tx #(
.ID (ID),
.DDS_TYPE (DAC_DDS_TYPE),
.DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
i_tx (
.dac_clk (dac_clk),

1
library/axi_ad9963/axi_ad9963_ip.tcl
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@ -17,6 +17,7 @@ adi_ip_files axi_ad9963 [list \
"$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_2.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \

15
library/axi_ad9963/axi_ad9963_tx.v
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@ -40,8 +40,9 @@ module axi_ad9963_tx #(
// parameters
parameter ID = 0,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 14,
parameter DAC_DDS_CORDIC_PHASE_DW = 13,
parameter DATAPATH_DISABLE = 0) (
// dac interface
@ -122,8 +123,9 @@ module axi_ad9963_tx #(
axi_ad9963_tx_channel #(
.CHANNEL_ID (0),
.Q_OR_I_N (0),
.DDS_TYPE (DDS_TYPE),
.DDS_CORDIC_DW (DDS_CORDIC_DW),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_tx_channel_0 (
.dac_clk (dac_clk),
@ -153,8 +155,9 @@ module axi_ad9963_tx #(
axi_ad9963_tx_channel #(
.CHANNEL_ID (1),
.Q_OR_I_N (1),
.DDS_TYPE (DDS_TYPE),
.DDS_CORDIC_DW (DDS_CORDIC_DW),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_tx_channel_1 (
.dac_clk (dac_clk),

63
library/axi_ad9963/axi_ad9963_tx_channel.v
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@ -41,8 +41,9 @@ module axi_ad9963_tx_channel #(
parameter CHANNEL_ID = 32'h0,
parameter Q_OR_I_N = 0,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 14,
parameter DAC_DDS_CORDIC_PHASE_DW = 13,
parameter DATAPATH_DISABLE = 0) (
// dac interface
@ -87,11 +88,6 @@ module axi_ad9963_tx_channel #(
reg [23:0] dac_test_data = 'd0;
reg [15:0] dac_test_counter = 'd0;
reg [15:0] dac_pat_data = 'd0;
reg [15:0] dac_dds_phase_0 = 'd0;
reg [15:0] dac_dds_phase_1 = 'd0;
reg [15:0] dac_dds_incr_0 = 'd0;
reg [15:0] dac_dds_incr_1 = 'd0;
reg [15:0] dac_dds_data = 'd0;
// internal signals
@ -148,7 +144,7 @@ module axi_ad9963_tx_channel #(
4'h3: dac_data_out <= 12'd0;
4'h2: dac_data_out <= dma_data[15:4];
4'h1: dac_data_out <= dac_pat_data[15:4];
default: dac_data_out <= dac_dds_data[15:4];
default: dac_data_out <= dac_dds_data_s;
endcase
end
@ -173,13 +169,6 @@ module axi_ad9963_tx_channel #(
end
end
// dds
generate
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_s = 16'd0;
end else begin
// pattern
always @(posedge dac_clk) begin
if (dac_data_sync == 1'b1) begin
@ -199,36 +188,28 @@ module axi_ad9963_tx_channel #(
end
end
always @(posedge dac_clk) begin
if (dac_data_sync == 1'b1) begin
dac_dds_phase_0 <= dac_dds_init_1_s;
dac_dds_phase_1 <= dac_dds_init_2_s;
dac_dds_incr_0 <= dac_dds_incr_1_s;
dac_dds_incr_1 <= dac_dds_incr_2_s;
dac_dds_data <= 16'd0;
end else if (dac_valid == 1'b1) begin
dac_dds_phase_0 <= dac_dds_phase_0 + dac_dds_incr_0;
dac_dds_phase_1 <= dac_dds_phase_1 + dac_dds_incr_1;
dac_dds_incr_0 <= dac_dds_incr_0;
dac_dds_incr_1 <= dac_dds_incr_1;
dac_dds_data <= dac_dds_data_s;
end
end
// dds
ad_dds #(
.DISABLE (0),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
.DISABLE (DATAPATH_DISABLE),
.DDS_DW (12),
.PHASE_DW (16),
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.CLK_RATIO (1))
i_dds (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_s));
end
endgenerate
.dac_dds_format (dac_dds_format),
.dac_data_sync (dac_data_sync),
.dac_valid (1'b1),
.tone_1_scale (dac_dds_scale_1_s),
.tone_2_scale (dac_dds_scale_2_s),
.tone_1_init_offset (dac_dds_init_1_s),
.tone_2_init_offset (dac_dds_init_2_s),
.tone_1_freq_word (dac_dds_init_2_s),
.tone_2_freq_word (dac_dds_incr_2_s),
.dac_dds_data (dac_dds_data_s));
// single channel processor