diff --git a/projects/pmods/cftl_xil_common/cftl_bd.tcl b/projects/pmods/cftl_xil_common/cftl_bd.tcl new file mode 100755 index 000000000..0e78916bf --- /dev/null +++ b/projects/pmods/cftl_xil_common/cftl_bd.tcl @@ -0,0 +1,55 @@ + + # cftl + + set gpio_cftl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_cftl ] + set iic_cftl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_cftl ] + set spi1_cftl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 spi1_cftl ] + set spi_cftl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 spi_cftl ] + + # gpio_cftl + + set axi_gpio_cftl [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_cftl ] + set_property -dict [ list CONFIG.C_GPIO_WIDTH {2} ] $axi_gpio_cftl + + # spi0, spi1, iic + + set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} ] $sys_ps7 + set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} ] $sys_ps7 + set_property -dict [list CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} ] $sys_ps7 + + # interconnect + + set_property -dict [list CONFIG.NUM_MI {8}] $axi_cpu_interconnect + + # gpio_cftl + + connect_bd_intf_net -intf_net axi_gpio_cftl_GPIO [get_bd_intf_ports gpio_cftl] [get_bd_intf_pins axi_gpio_cftl/GPIO] + + # iic cftl + + connect_bd_intf_net -intf_net sys_ps7_IIC_0 [get_bd_intf_ports iic_cftl] [get_bd_intf_pins sys_ps7/IIC_0] + + # spi0 cftl + + connect_bd_intf_net -intf_net sys_ps7_SPI_0 [get_bd_intf_ports spi_cftl] [get_bd_intf_pins sys_ps7/SPI_0] + + # spi1 cftl + + connect_bd_intf_net -intf_net sys_ps7_SPI_1 [get_bd_intf_ports spi1_cftl] [get_bd_intf_pins sys_ps7/SPI_1] + + # interconnect (cpu) + + connect_bd_intf_net -intf_net axi_cpu_interconnect_M07_AXI [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_gpio_cftl/S_AXI] + + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source + + # interconnects (gpio_cftl) + + connect_bd_net -net sys_100m_clk [get_bd_pins axi_gpio_cftl/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_gpio_cftl/s_axi_aresetn] $sys_100m_resetn_source + + + # address map + + create_bd_addr_seg -range 0x10000 -offset 0x41200000 [get_bd_addr_spaces sys_ps7/Data] [get_bd_addr_segs axi_gpio_cftl/S_AXI/Reg] SEG_axi_gpio_cftl_Reg diff --git a/projects/pmods/cftl_xil_zed/system_bd.tcl b/projects/pmods/cftl_xil_zed/system_bd.tcl new file mode 100755 index 000000000..5a6850b82 --- /dev/null +++ b/projects/pmods/cftl_xil_zed/system_bd.tcl @@ -0,0 +1,4 @@ + + source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl + source ../cftl_xil_common/cftl_bd.tcl + diff --git a/projects/pmods/cftl_xil_zed/system_constr.xdc b/projects/pmods/cftl_xil_zed/system_constr.xdc new file mode 100755 index 000000000..7d7ee9ba5 --- /dev/null +++ b/projects/pmods/cftl_xil_zed/system_constr.xdc @@ -0,0 +1,18 @@ +# CFTL + +set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports spi_cftl_ss_io]; # "JA1" +set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS33} [get_ports spi_cftl_mosi_io]; # "JA2" +set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS33} [get_ports spi_cftl_miso_io]; # "JA3" +set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports spi_cftl_sck_io]; # "JA4" +set_property -dict {PACKAGE_PIN AB9 IOSTANDARD LVCMOS33} [get_ports gpio_cftl_tri_io[0]]; # "JA9" +set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports gpio_cftl_tri_io[1]]; # "JA10" + + +set_property -dict {PACKAGE_PIN W12 IOSTANDARD LVCMOS33} [get_ports iic_cftl_scl_io]; # "JB1" +set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS33} [get_ports iic_cftl_sda_io]; # "JB2" + +set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports spi1_cftl_ss_io]; # "JC1_P" +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports spi1_cftl_mosi_io]; # "JC1_N" +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33} [get_ports spi1_cftl_miso_io]; # "JC2_P" +set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS33} [get_ports spi1_cftl_sck_io]; # "JC2_N" +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports spi1_cftl_ss1_o]; # "JC4_N" diff --git a/projects/pmods/cftl_xil_zed/system_project.tcl b/projects/pmods/cftl_xil_zed/system_project.tcl new file mode 100755 index 000000000..1af7d3e46 --- /dev/null +++ b/projects/pmods/cftl_xil_zed/system_project.tcl @@ -0,0 +1,12 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl + +adi_project_create cftl_xil_zed +adi_project_files cftl_xil_zed [list \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ] + +adi_project_run cftl_xil_zed diff --git a/projects/pmods/cftl_xil_zed/system_top.v b/projects/pmods/cftl_xil_zed/system_top.v new file mode 100755 index 000000000..4f141492c --- /dev/null +++ b/projects/pmods/cftl_xil_zed/system_top.v @@ -0,0 +1,280 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2015(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + i2s_mclk, + i2s_bclk, + i2s_lrclk, + i2s_sdata_out, + i2s_sdata_in, + + spdif, + + iic_scl, + iic_sda, + iic_mux_scl, + iic_mux_sda, + + iic_cftl_scl_io, + iic_cftl_sda_io, + + spi_cftl_mosi_io, + spi_cftl_miso_io, + spi_cftl_sck_io, + spi_cftl_ss_io, + + spi1_cftl_mosi_io, + spi1_cftl_miso_io, + spi1_cftl_sck_io, + spi1_cftl_ss_io, + spi1_cftl_ss1_o, + + gpio_cftl_tri_io, + + otg_vbusoc); + + inout [14:0] DDR_addr; + inout [ 2:0] DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [ 3:0] DDR_dm; + inout [31:0] DDR_dq; + inout [ 3:0] DDR_dqs_n; + inout [ 3:0] DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0] FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + + inout [31:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [15:0] hdmi_data; + + output spdif; + + output i2s_mclk; + output i2s_bclk; + output i2s_lrclk; + output i2s_sdata_out; + input i2s_sdata_in; + + inout iic_scl; + inout iic_sda; + inout [ 1:0] iic_mux_scl; + inout [ 1:0] iic_mux_sda; + + inout iic_cftl_scl_io; + inout iic_cftl_sda_io; + + inout spi_cftl_mosi_io; + inout spi_cftl_miso_io; + inout spi_cftl_sck_io; + inout spi_cftl_ss_io; + + inout spi1_cftl_mosi_io; + inout spi1_cftl_miso_io; + inout spi1_cftl_sck_io; + inout spi1_cftl_ss_io; + output spi1_cftl_ss1_o; + + inout [ 1:0] gpio_cftl_tri_io; + + input otg_vbusoc; + + // internal signals + + wire [31:0] gpio_i; + wire [31:0] gpio_o; + wire [31:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + wire [15:0] ps_intrs; + + // instantiations + + ad_iobuf #( + .DATA_WIDTH(32)) + i_gpio_bd ( + .dt(gpio_t), + .di(gpio_o), + .do(gpio_i), + .dio(gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH(2)) + i_iic_mux_scl ( + .dt({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .di(iic_mux_scl_o_s), + .do(iic_mux_scl_i_s), + .dio(iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH(2)) + i_iic_mux_sda ( + .dt({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .di(iic_mux_sda_o_s), + .do(iic_mux_sda_i_s), + .dio(iic_mux_sda)); + + system_wrapper i_system_wrapper ( + .DDR_addr (DDR_addr), + .DDR_ba (DDR_ba), + .DDR_cas_n (DDR_cas_n), + .DDR_ck_n (DDR_ck_n), + .DDR_ck_p (DDR_ck_p), + .DDR_cke (DDR_cke), + .DDR_cs_n (DDR_cs_n), + .DDR_dm (DDR_dm), + .DDR_dq (DDR_dq), + .DDR_dqs_n (DDR_dqs_n), + .DDR_dqs_p (DDR_dqs_p), + .DDR_odt (DDR_odt), + .DDR_ras_n (DDR_ras_n), + .DDR_reset_n (DDR_reset_n), + .DDR_we_n (DDR_we_n), + .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), + .FIXED_IO_mio (FIXED_IO_mio), + .FIXED_IO_ps_clk (FIXED_IO_ps_clk), + .FIXED_IO_ps_porb (FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), + .GPIO_I (gpio_i), + .GPIO_O (gpio_o), + .GPIO_T (gpio_t), + + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_cftl_scl_io(iic_cftl_scl_io), + .iic_cftl_sda_io(iic_cftl_sda_io), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_I (iic_mux_scl_i_s), + .iic_mux_scl_O (iic_mux_scl_o_s), + .iic_mux_scl_T (iic_mux_scl_t_s), + .iic_mux_sda_I (iic_mux_sda_i_s), + .iic_mux_sda_O (iic_mux_sda_o_s), + .iic_mux_sda_T (iic_mux_sda_t_s), + .ps_intr_10 (ps_intrs[10]), + .ps_intr_11 (ps_intrs[11]), + .ps_intr_12 (ps_intrs[12]), + .ps_intr_13 (ps_intrs[13]), + .ps_intr_4 (ps_intrs[4]), + .ps_intr_5 (ps_intrs[5]), + .ps_intr_6 (ps_intrs[6]), + .ps_intr_7 (ps_intrs[7]), + .ps_intr_8 (ps_intrs[8]), + .ps_intr_9 (ps_intrs[9]), + .iic_fmc_intr(ps_intrs[11]), + .spi_cftl_io0_io(spi_cftl_mosi_io), + .spi_cftl_io1_io(spi_cftl_miso_io), + .spi_cftl_sck_io(spi_cftl_sck_io), + .spi_cftl_ss_io(spi_cftl_ss_io), + .spi1_cftl_io0_io(spi1_cftl_mosi_io), + .spi1_cftl_io1_io(spi1_cftl_miso_io), + .spi1_cftl_sck_io(spi1_cftl_sck_io), + .spi1_cftl_ss1_o(spi1_cftl_ss1_o), + .spi1_cftl_ss_io(spi1_cftl_ss_io), + .gpio_cftl_tri_io(gpio_cftl_tri_io), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif)); + +endmodule + +// *************************************************************************** +// ***************************************************************************