cftl_xil_zed: Initial commit for common platform used with CFTL circuits
This common platform uses PS7 SPI and I2C to communicate with different chips. On different connectors different pin configurations are supported: - On connector JA, a spi interface and a 2 pin GPIO - On connector JB, a I2C interface - On connector JC, a spi interface with 2 chip selectsmain
Adrian Costina
parent
a170ebfb82
commit
51e6d0888a
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@ -0,0 +1,55 @@
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# cftl
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set gpio_cftl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_cftl ]
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set iic_cftl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_cftl ]
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set spi1_cftl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 spi1_cftl ]
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set spi_cftl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 spi_cftl ]
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# gpio_cftl
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set axi_gpio_cftl [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_cftl ]
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set_property -dict [ list CONFIG.C_GPIO_WIDTH {2} ] $axi_gpio_cftl
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# spi0, spi1, iic
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} ] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} ] $sys_ps7
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set_property -dict [list CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} ] $sys_ps7
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# interconnect
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set_property -dict [list CONFIG.NUM_MI {8}] $axi_cpu_interconnect
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# gpio_cftl
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connect_bd_intf_net -intf_net axi_gpio_cftl_GPIO [get_bd_intf_ports gpio_cftl] [get_bd_intf_pins axi_gpio_cftl/GPIO]
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# iic cftl
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connect_bd_intf_net -intf_net sys_ps7_IIC_0 [get_bd_intf_ports iic_cftl] [get_bd_intf_pins sys_ps7/IIC_0]
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# spi0 cftl
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connect_bd_intf_net -intf_net sys_ps7_SPI_0 [get_bd_intf_ports spi_cftl] [get_bd_intf_pins sys_ps7/SPI_0]
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# spi1 cftl
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connect_bd_intf_net -intf_net sys_ps7_SPI_1 [get_bd_intf_ports spi1_cftl] [get_bd_intf_pins sys_ps7/SPI_1]
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# interconnect (cpu)
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connect_bd_intf_net -intf_net axi_cpu_interconnect_M07_AXI [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_gpio_cftl/S_AXI]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
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# interconnects (gpio_cftl)
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_gpio_cftl/s_axi_aclk] $sys_100m_clk_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_gpio_cftl/s_axi_aresetn] $sys_100m_resetn_source
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# address map
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create_bd_addr_seg -range 0x10000 -offset 0x41200000 [get_bd_addr_spaces sys_ps7/Data] [get_bd_addr_segs axi_gpio_cftl/S_AXI/Reg] SEG_axi_gpio_cftl_Reg
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
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source ../cftl_xil_common/cftl_bd.tcl
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# CFTL
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set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports spi_cftl_ss_io]; # "JA1"
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set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS33} [get_ports spi_cftl_mosi_io]; # "JA2"
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set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS33} [get_ports spi_cftl_miso_io]; # "JA3"
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set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports spi_cftl_sck_io]; # "JA4"
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set_property -dict {PACKAGE_PIN AB9 IOSTANDARD LVCMOS33} [get_ports gpio_cftl_tri_io[0]]; # "JA9"
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set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports gpio_cftl_tri_io[1]]; # "JA10"
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set_property -dict {PACKAGE_PIN W12 IOSTANDARD LVCMOS33} [get_ports iic_cftl_scl_io]; # "JB1"
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set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS33} [get_ports iic_cftl_sda_io]; # "JB2"
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set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports spi1_cftl_ss_io]; # "JC1_P"
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set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports spi1_cftl_mosi_io]; # "JC1_N"
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set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33} [get_ports spi1_cftl_miso_io]; # "JC2_P"
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set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS33} [get_ports spi1_cftl_sck_io]; # "JC2_N"
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set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports spi1_cftl_ss1_o]; # "JC4_N"
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@ -0,0 +1,12 @@
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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adi_project_create cftl_xil_zed
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adi_project_files cftl_xil_zed [list \
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"system_top.v" \
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"system_constr.xdc" \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ]
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adi_project_run cftl_xil_zed
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2015(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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DDR_addr,
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DDR_ba,
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DDR_cas_n,
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DDR_ck_n,
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DDR_ck_p,
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DDR_cke,
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DDR_cs_n,
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DDR_dm,
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DDR_dq,
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DDR_dqs_n,
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DDR_dqs_p,
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DDR_odt,
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DDR_ras_n,
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DDR_reset_n,
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DDR_we_n,
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FIXED_IO_ddr_vrn,
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FIXED_IO_ddr_vrp,
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FIXED_IO_mio,
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FIXED_IO_ps_clk,
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FIXED_IO_ps_porb,
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FIXED_IO_ps_srstb,
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gpio_bd,
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hdmi_out_clk,
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hdmi_vsync,
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hdmi_hsync,
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hdmi_data_e,
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hdmi_data,
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i2s_mclk,
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i2s_bclk,
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i2s_lrclk,
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i2s_sdata_out,
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i2s_sdata_in,
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spdif,
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iic_scl,
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iic_sda,
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iic_mux_scl,
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iic_mux_sda,
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iic_cftl_scl_io,
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iic_cftl_sda_io,
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spi_cftl_mosi_io,
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spi_cftl_miso_io,
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spi_cftl_sck_io,
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spi_cftl_ss_io,
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spi1_cftl_mosi_io,
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spi1_cftl_miso_io,
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spi1_cftl_sck_io,
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spi1_cftl_ss_io,
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spi1_cftl_ss1_o,
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gpio_cftl_tri_io,
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otg_vbusoc);
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inout [14:0] DDR_addr;
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inout [ 2:0] DDR_ba;
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inout DDR_cas_n;
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inout DDR_ck_n;
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inout DDR_ck_p;
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inout DDR_cke;
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inout DDR_cs_n;
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inout [ 3:0] DDR_dm;
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inout [31:0] DDR_dq;
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inout [ 3:0] DDR_dqs_n;
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inout [ 3:0] DDR_dqs_p;
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inout DDR_odt;
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inout DDR_ras_n;
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inout DDR_reset_n;
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inout DDR_we_n;
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inout FIXED_IO_ddr_vrn;
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inout FIXED_IO_ddr_vrp;
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inout [53:0] FIXED_IO_mio;
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inout FIXED_IO_ps_clk;
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inout FIXED_IO_ps_porb;
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inout FIXED_IO_ps_srstb;
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inout [31:0] gpio_bd;
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output hdmi_out_clk;
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output hdmi_vsync;
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output hdmi_hsync;
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output hdmi_data_e;
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output [15:0] hdmi_data;
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output spdif;
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output i2s_mclk;
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output i2s_bclk;
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output i2s_lrclk;
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output i2s_sdata_out;
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input i2s_sdata_in;
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inout iic_scl;
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inout iic_sda;
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inout [ 1:0] iic_mux_scl;
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inout [ 1:0] iic_mux_sda;
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inout iic_cftl_scl_io;
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inout iic_cftl_sda_io;
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inout spi_cftl_mosi_io;
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inout spi_cftl_miso_io;
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inout spi_cftl_sck_io;
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inout spi_cftl_ss_io;
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inout spi1_cftl_mosi_io;
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inout spi1_cftl_miso_io;
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inout spi1_cftl_sck_io;
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inout spi1_cftl_ss_io;
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output spi1_cftl_ss1_o;
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inout [ 1:0] gpio_cftl_tri_io;
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input otg_vbusoc;
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// internal signals
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wire [31:0] gpio_i;
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wire [31:0] gpio_o;
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wire [31:0] gpio_t;
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wire [ 1:0] iic_mux_scl_i_s;
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wire [ 1:0] iic_mux_scl_o_s;
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wire iic_mux_scl_t_s;
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wire [ 1:0] iic_mux_sda_i_s;
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wire [ 1:0] iic_mux_sda_o_s;
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wire iic_mux_sda_t_s;
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wire [15:0] ps_intrs;
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// instantiations
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ad_iobuf #(
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.DATA_WIDTH(32))
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i_gpio_bd (
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.dt(gpio_t),
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.di(gpio_o),
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.do(gpio_i),
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.dio(gpio_bd));
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ad_iobuf #(
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.DATA_WIDTH(2))
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i_iic_mux_scl (
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.dt({iic_mux_scl_t_s, iic_mux_scl_t_s}),
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.di(iic_mux_scl_o_s),
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.do(iic_mux_scl_i_s),
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.dio(iic_mux_scl));
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ad_iobuf #(
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.DATA_WIDTH(2))
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i_iic_mux_sda (
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.dt({iic_mux_sda_t_s, iic_mux_sda_t_s}),
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.di(iic_mux_sda_o_s),
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.do(iic_mux_sda_i_s),
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.dio(iic_mux_sda));
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system_wrapper i_system_wrapper (
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.DDR_addr (DDR_addr),
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.DDR_ba (DDR_ba),
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.DDR_cas_n (DDR_cas_n),
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.DDR_ck_n (DDR_ck_n),
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.DDR_ck_p (DDR_ck_p),
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.DDR_cke (DDR_cke),
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.DDR_cs_n (DDR_cs_n),
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.DDR_dm (DDR_dm),
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.DDR_dq (DDR_dq),
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.DDR_dqs_n (DDR_dqs_n),
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.DDR_dqs_p (DDR_dqs_p),
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.DDR_odt (DDR_odt),
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.DDR_ras_n (DDR_ras_n),
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.DDR_reset_n (DDR_reset_n),
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.DDR_we_n (DDR_we_n),
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.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
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.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
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.FIXED_IO_mio (FIXED_IO_mio),
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.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
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.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
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.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
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.GPIO_I (gpio_i),
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.GPIO_O (gpio_o),
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.GPIO_T (gpio_t),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.i2s_bclk (i2s_bclk),
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.i2s_lrclk (i2s_lrclk),
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.i2s_mclk (i2s_mclk),
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.i2s_sdata_in (i2s_sdata_in),
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.i2s_sdata_out (i2s_sdata_out),
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.iic_cftl_scl_io(iic_cftl_scl_io),
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.iic_cftl_sda_io(iic_cftl_sda_io),
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.iic_fmc_scl_io (iic_scl),
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.iic_fmc_sda_io (iic_sda),
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.iic_mux_scl_I (iic_mux_scl_i_s),
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.iic_mux_scl_O (iic_mux_scl_o_s),
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.iic_mux_scl_T (iic_mux_scl_t_s),
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.iic_mux_sda_I (iic_mux_sda_i_s),
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.iic_mux_sda_O (iic_mux_sda_o_s),
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.iic_mux_sda_T (iic_mux_sda_t_s),
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.ps_intr_10 (ps_intrs[10]),
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.ps_intr_11 (ps_intrs[11]),
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.ps_intr_12 (ps_intrs[12]),
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.ps_intr_13 (ps_intrs[13]),
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.ps_intr_4 (ps_intrs[4]),
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.ps_intr_5 (ps_intrs[5]),
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.ps_intr_6 (ps_intrs[6]),
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.ps_intr_7 (ps_intrs[7]),
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.ps_intr_8 (ps_intrs[8]),
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.ps_intr_9 (ps_intrs[9]),
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.iic_fmc_intr(ps_intrs[11]),
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.spi_cftl_io0_io(spi_cftl_mosi_io),
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.spi_cftl_io1_io(spi_cftl_miso_io),
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.spi_cftl_sck_io(spi_cftl_sck_io),
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.spi_cftl_ss_io(spi_cftl_ss_io),
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.spi1_cftl_io0_io(spi1_cftl_mosi_io),
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.spi1_cftl_io1_io(spi1_cftl_miso_io),
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.spi1_cftl_sck_io(spi1_cftl_sck_io),
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.spi1_cftl_ss1_o(spi1_cftl_ss1_o),
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.spi1_cftl_ss_io(spi1_cftl_ss_io),
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.gpio_cftl_tri_io(gpio_cftl_tri_io),
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.otg_vbusoc (otg_vbusoc),
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.spdif (spdif));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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Reference in New Issue