common/a10soc- add project create tcl procedure
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f278b6e6c9
commit
5176e427a1
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@ -1,14 +1,4 @@
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# a10soc carrier defaults
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# device settings
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set_global_assignment -name FAMILY "Arria 10"
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set_global_assignment -name DEVICE 10AS066N3F40E2SGE2
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# ignored warnings and such
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set_global_assignment -name MESSAGE_DISABLE 17951 ; ## disable unused RX channels message
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set_global_assignment -name MESSAGE_DISABLE 18655 ; ## disable unused TX channels message
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# clocks and resets
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# clocks and resets
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set_location_assignment PIN_AM10 -to sys_clk
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set_location_assignment PIN_AM10 -to sys_clk
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@ -259,6 +249,3 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio[1]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio[2]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio[2]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio[3]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio[3]
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# source defaults
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source $ad_hdl_dir/projects/common/altera/sys_gen.tcl
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@ -1,12 +1,9 @@
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# a10soc carrier qsys
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package require qsys
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set_module_property NAME {system_bd}
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set_project_property DEVICE_FAMILY {Arria 10}
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set_project_property DEVICE {10AS066N3F40E2SGE2}
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set system_type a10soc
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set system_type a10soc
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# clock-&-reset
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add_instance sys_clk clock_source
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add_instance sys_clk clock_source
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add_interface sys_clk clock sink
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add_interface sys_clk clock sink
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set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
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set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
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