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jesd_rst_gen:constraints: Remove invalid false path definitions 

The constraint where added to remove timing problems on the reset path.

The constraint paths do not match anymore. The resets are used in a synchronous
way so we don't need the timing exceptions anyway.

Projects affected by this change:
  - daq3
  - adrv9739
  - ad6676evb
  - fmcadc5
  - daq2/kcu105
  - fmcadc2
  - adrv9371x
  - fmcomms11/zc706
  - fmcjesdadc1
main
AndreiGrozav 2018-02-14 13:02:56 +00:00 committed by István Csomortáni
parent 2356694a50
commit 502989c25f
17 changed files with 3 additions and 54 deletions
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5
projects/ad6676evb/vc707/system_constr.xdc
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@ -33,8 +33,3 @@ set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_agc4]
create_clock -name rx_ref_clk -period 5.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]

6
projects/ad6676evb/zc706/system_constr.xdc
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@ -32,9 +32,3 @@ set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_agc4
create_clock -name rx_ref_clk -period 5.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]

3
projects/adrv9371x/kcu105/system_constr.xdc
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@ -87,6 +87,3 @@ set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *
set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *util_ad9371_xcvr/inst/i_xch_2/i_gthe3_channel}]
set_property LOC GTHE3_CHANNEL_X0Y19 [get_cells -hierarchical -filter {NAME =~ *util_ad9371_xcvr/inst/i_xch_3/i_gthe3_channel}]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_tx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_os_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]

4
projects/adrv9371x/zc706/system_constr.xdc
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@ -74,7 +74,3 @@ create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/syste
create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
create_clock -name rx_os_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_2/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_tx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_os_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]

5
projects/adrv9371x/zcu102/system_constr.xdc
View File

@ -58,14 +58,11 @@ set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hierarchical -filter {NAME =~ *
create_clock -name tx_ref_clk -period 8.00 [get_ports ref_clk0_p]
create_clock -name rx_ref_clk -period 8.00 [get_ports ref_clk1_p]
create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
create_clock -name rx_os_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_2/i_gthe4_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_tx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_os_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
# pin assignments below are for reference only and are ignored by the tool!
# set_property -dict {PACKAGE_PIN G8 } [get_ports ref_clk0_p] ; ## D04 FMC_HPC0_GBTCLK0_M2C_C_P

5
projects/adrv9379/zc706/system_constr.xdc
View File

@ -77,8 +77,3 @@ create_clock -name rx_ref_clk -period 4.00 [get_ports ref_clk1_p]
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_ad9379_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_ad9379_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
create_clock -name rx_os_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_ad9379_xcvr/inst/i_xch_2/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9379_rx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9379_tx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9379_rx_os_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]

3
projects/daq2/kcu105/system_constr.xdc
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@ -67,6 +67,3 @@ set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *
set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_2/i_gthe3_channel}]
set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_3/i_gthe3_channel}]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9144_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]

3
projects/daq3/kcu105/system_constr.xdc
View File

@ -67,6 +67,3 @@ set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *
set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_2/i_gthe3_channel}]
set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_3/i_gthe3_channel}]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9152_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]

4
projects/daq3/zc706/system_constr.xdc
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@ -57,6 +57,6 @@ create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p]
create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9152_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
#set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
#set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9152_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]

3
projects/daq3/zcu102/system_constr.xdc
View File

@ -48,9 +48,6 @@ create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p]
create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9152_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
# pin assignments below are for reference only and are ignored by the tool!
# set_property -dict {PACKAGE_PIN L8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC0_GBTCLK1_M2C_C_P

1
projects/fmcadc2/vc707/system_constr.xdc
View File

@ -40,7 +40,6 @@ set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_fd]
create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcadc2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property IOB false [get_cells -hierarchical -filter {name =~ *SCK_O_NE_4_FDRE_INST}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}]

2
projects/fmcadc2/zc706/system_constr.xdc
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@ -40,8 +40,6 @@ set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_fd]
create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcadc2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]

3
projects/fmcadc5/vc707/system_constr.xdc
View File

@ -86,7 +86,4 @@ create_clock -name rx_ref_clk_0 -period 1.60 [get_ports rx_ref_clk_0_p]
create_clock -name rx_ref_clk_1 -period 1.60 [get_ports rx_ref_clk_1_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcadc5_0_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_0_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
set_property IOB false [get_cells -hierarchical -filter {name =~ *SCK_O_NE_4_FDRE_INST}]

2
projects/fmcjesdadc1/kc705/system_constr.xdc
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@ -23,8 +23,6 @@ set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports spi_sdio
create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcjesdadc1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]

2
projects/fmcjesdadc1/vc707/system_constr.xdc
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@ -23,8 +23,6 @@ set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS18} [get_ports spi_sdio
create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcjesdadc1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]

2
projects/fmcjesdadc1/zc706/system_constr.xdc
View File

@ -23,8 +23,6 @@ set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports spi_sdio
create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcjesdadc1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]

4
projects/fmcomms11/zc706/system_constr.xdc
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@ -64,7 +64,3 @@ set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports ad9162_i
create_clock -name rx_ref_clk -period 6.40 [get_ports trx_ref_clk_p]
create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_fmcomms11_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcomms11_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9162_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]