system_id: added axi_sysid ip core and tcl
Sergiu Arpadi
sarpadi
parent
ab3d43be71
commit
4fe5f007cb
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@ -0,0 +1,13 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_sysid
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GENERIC_DEPS += ../common/up_axi.v
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GENERIC_DEPS += axi_sysid.v
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XILINX_DEPS += axi_sysid_ip.tcl
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include ../scripts/library.mk
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@ -0,0 +1,135 @@
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`timescale 1ns / 1ps
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module sys_id #(
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parameter ROM_WIDTH = 32,
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parameter ROM_ADDR_BITS = 9)(
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//axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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input [2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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input [2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready,
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input [ROM_WIDTH-1:0] sys_rom_data,
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input [ROM_WIDTH-1:0] pr_rom_data,
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output [ROM_ADDR_BITS-1:0] rom_addr);
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localparam AXI_ADDRESS_WIDTH = 12;
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localparam [31:0] CORE_VERSION = {16'h0001, /* MAJOR */
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8'h00, /* MINOR */
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8'h00}; /* PATCH */
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localparam [31:0] CORE_MAGIC = 32'h53594944; // SYID
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reg up_wack = 'd0;
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reg [31:0] up_rdata_s = 'd0;
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reg up_rack_s = 'd0;
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reg up_rreq_s_d = 'd0;
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reg [31:0] up_scratch = 'd0;
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wire up_clk;
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wire up_rstn;
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wire up_rreq_s;
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wire [(ROM_ADDR_BITS+1):0] up_raddr_s;
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wire up_wreq_s;
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wire [(ROM_ADDR_BITS+1):0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] rom_data_s;
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign rom_addr = up_raddr_s [ROM_ADDR_BITS-1:0];
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assign rom_data_s = (up_raddr_s [ROM_ADDR_BITS + 1'h1: ROM_ADDR_BITS] == 2'h1) ? sys_rom_data :
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(up_raddr_s [ROM_ADDR_BITS + 1'h1: ROM_ADDR_BITS] == 2'h2) ? pr_rom_data : 'h0;
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up_axi #(
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.AXI_ADDRESS_WIDTH(ROM_ADDR_BITS+4))
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i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr[ROM_ADDR_BITS+3:0]),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr[ROM_ADDR_BITS+3:0]),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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//delaying data read with 1 tck to compensate for the ROM latency
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always @(posedge up_clk) begin
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up_rreq_s_d <= up_rreq_s;
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end
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//axi registers read
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always @(posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_rack_s <= 'd0;
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up_rdata_s <= 'd0;
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end else begin
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up_rack_s <= up_rreq_s_d;
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if (up_rreq_s_d == 1'b1) begin
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case (up_raddr_s)
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8'h00: up_rdata_s <= CORE_VERSION;
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8'h01: up_rdata_s <= 0;
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8'h02: up_rdata_s <= up_scratch;
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8'h03: up_rdata_s <= CORE_MAGIC;
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8'h10: up_rdata_s <= ROM_ADDR_BITS;
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default: begin
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up_rdata_s <= rom_data_s;
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end
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endcase
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end else begin
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up_rdata_s <= 32'd0;
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end
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end
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end
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//axi registers write
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always @(posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_wack <= 'd0;
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up_scratch <= 'd0;
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end else begin
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h02)) begin
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up_scratch <= up_wdata_s;
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end
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end
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end
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endmodule
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@ -0,0 +1,14 @@
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# ip
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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adi_ip_create axi_sysid
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adi_ip_files axi_sysid [list \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"axi_sysid.v"]
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adi_ip_properties axi_sysid
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set cc [ipx::current_core]
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ipx::save_core $cc
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@ -0,0 +1,5 @@
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=============
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AXI System ID
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=============
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System Identification IP core
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@ -0,0 +1,12 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := sysid_rom
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GENERIC_DEPS += sysid_rom.v
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XILINX_DEPS += sysid_rom_ip.tcl
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include ../scripts/library.mk
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@ -0,0 +1,22 @@
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`timescale 1ns / 1ps
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module sysid_rom#(
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parameter ROM_WIDTH = 32,
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parameter ROM_ADDR_BITS = 6,
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parameter PATH_TO_FILE = "path_to_mem_init_file" )(
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input clk,
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input [ROM_ADDR_BITS-1:0] rom_addr,
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output reg [ROM_WIDTH-1:0] rom_data);
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reg [ROM_WIDTH-1:0] lut_rom [(2**ROM_ADDR_BITS)-1:0];
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initial begin
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$readmemh(PATH_TO_FILE, lut_rom, 0, (2**ROM_ADDR_BITS)-1);
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end
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always @(posedge clk) begin
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rom_data = lut_rom[rom_addr];
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end
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endmodule
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@ -0,0 +1,13 @@
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# ip
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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adi_ip_create sysid_rom
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adi_ip_files sysid_rom [list \
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"sysid_rom.v"]
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adi_ip_properties_lite sysid_rom
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set cc [ipx::current_core]
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ipx::save_core $cc
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@ -14,6 +14,8 @@ LIB_DEPS += axi_dmac
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LIB_DEPS += axi_hdmi_tx
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LIB_DEPS += axi_i2s_adi
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LIB_DEPS += axi_spdif_tx
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LIB_DEPS += axi_sysid
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LIB_DEPS += sysid_rom
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LIB_DEPS += util_i2c_mixer
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include ../../scripts/project-xilinx.mk
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@ -1,3 +1,10 @@
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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set sys_cstring "sys rom custom string placeholder"
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sysid_gen_sys_init_file $sys_cstring
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@ -257,6 +257,14 @@ ad_connect sys_ps7/DMA2_REQ axi_i2s_adi/DMA_REQ_RX
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ad_connect sys_ps7/DMA2_ACK axi_i2s_adi/DMA_ACK_RX
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ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_RX_RSTN
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# system id
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ad_ip_instance axi_sysid axi_sysid_0
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ad_ip_instance sysid_rom rom_sys_0
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ad_connect axi_sysid_0/rom_addr rom_sys_0/rom_addr
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ad_connect axi_sysid_0/sys_rom_data rom_sys_0/rom_data
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# interrupts
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ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P
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@ -280,12 +288,13 @@ ad_connect sys_concat_intc/In0 GND
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# interconnects and address mapping
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ad_cpu_interconnect 0x41600000 axi_iic_main
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ad_cpu_interconnect 0x45000000 axi_sysid_0
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ad_cpu_interconnect 0x79000000 axi_hdmi_clkgen
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ad_cpu_interconnect 0x43000000 axi_hdmi_dma
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ad_cpu_interconnect 0x70e00000 axi_hdmi_core
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ad_cpu_interconnect 0x75c00000 axi_spdif_tx_core
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ad_cpu_interconnect 0x77600000 axi_i2s_adi
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ad_cpu_interconnect 0x41620000 axi_iic_fmc
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ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
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ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/m_src_axi
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@ -786,3 +786,191 @@ proc ad_cpu_interrupt {p_ps_index p_mb_index p_name} {
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}
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}
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## Converts a string input to hex and adds whitespace as padding to obtain the size defined by
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# the blocksize parameter.
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#
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# \param[str] - string input
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# \param[blocksize] - size of hex output in bytes
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#
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# \return - hex
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#
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proc stringtohex {str blocksize} {
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binary scan $str H* hex
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return [format %0-[expr $blocksize * 2]s $hex]
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}
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## Generates the 8 bit checksum for the input hex string
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#
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# \param[hex] - string input
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#
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# \return - 8 bit checksum
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#
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proc checksum8bit {hex} {
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set chks 0
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for {set i 0} {$i < [string length $hex]} {incr i} {
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if { ($i+1) % 2 == 0} {
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set chks [expr $chks + "0x[string range $hex $i-1 $i]"]
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}
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}
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return [format %0.2x [expr 255 - [expr "0x[string range [format %0.2x $chks] [expr [string length [format %0.2x $chks]] -2] [expr [string length [format %0.2x $chks]] -1]]"] +1]]
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}
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## Flips the characters of a string, four at a time. Used to fix endianness.
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#
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# \param[str] - string input
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#
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# \return - string
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#
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proc hexstr_flip {str} {
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set fstr {}
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for {set i 0} {$i < [string length $str]} {incr i} {
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if { ($i+1) % 8 == 0} {
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set line [string range $str [expr $i - 7] $i]
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set fline {}
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for {set j 0} {$j < [string length $line]} {incr j} {
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if { ($j+1) % 2 == 0} {
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append fline [string reverse [append byte [string index $line $j]]]
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} else {
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set byte [string index $line $j]
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}
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}
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append fstr [string reverse $fline]
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}
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}
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return $fstr
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}
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## Generates a file used for initializing the system ROM.
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#
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# \param[custom_string] - string input
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#
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proc sysid_gen_sys_init_file {custom_string} {
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# git sha
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set no_git_err "fatal: not a git repository"
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if {[catch {exec git rev-parse HEAD} gitsha_string]} {
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if [expr [string match *$no_git_err* $gitsha_string] == 1] {
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set gitsha_string 0
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}
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}
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set gitsha_hex [hexstr_flip [stringtohex $gitsha_string 44]]
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#git clean
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set git_clean_string "f"
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if {$gitsha_string != 0} {
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set git_status [exec git status .]
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if [expr [string match *modified* $git_status] == 0] {
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set git_clean_string "t"
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}
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}
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set git_clean_hex [hexstr_flip [stringtohex $git_clean_string 4]]
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# vadj check
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set vadj_check_string "vadj"
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set vadj_check_hex [hexstr_flip [stringtohex $vadj_check_string 4]]
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# time and date
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set thetime [clock seconds]
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set timedate_hex [hexstr_flip [stringtohex $thetime 12]]
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# merge components
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set verh_hex {}
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set verh_size 448
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append verh_hex $gitsha_hex $git_clean_hex $vadj_check_hex $timedate_hex
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append verh_hex "00000000" [checksum8bit $verh_hex] "000000"
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set verh_hex [format %0-[expr [expr $verh_size] * 8]s $verh_hex]
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# common header
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# size in lines
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set table_size 16
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set comh_size [expr 8 * $table_size]
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# set version
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set comh_ver_hex "00000001"
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# project name
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set projname_hex [hexstr_flip [stringtohex [lindex [split [current_project] _] 0] 32]]
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# board name
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set boardname_hex [hexstr_flip [stringtohex [lindex [split [current_project] _] 1] 32]]
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# custom string
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set custom_hex [hexstr_flip [stringtohex $custom_string 64]]
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# pr offset
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# not used
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set pr_offset "00000000"
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# init - generate header
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set comh_hex {}
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append comh_hex $comh_ver_hex
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# offset for internal use area
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set offset $table_size
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append comh_hex [format %08s [format %0.2x $offset]]
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# offset for projname_hex
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set offset [expr $table_size + $verh_size]
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append comh_hex [format %08s [format %0.2x $offset]]
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# offset for boardname_hex
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set offset [expr $offset + [expr [string length $projname_hex] / 8]]
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append comh_hex [format %08s [format %0.2x $offset]]
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# offset for custom_hex
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set offset [expr $offset + [expr [string length $boardname_hex] / 8]]
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append comh_hex [format %08s [format %0.2x $offset]]
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# offset for pr custom string
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set offset $pr_offset
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append comh_hex [format %08s $offset]
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# pad header to match size and add checksum
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set comh_hex [format %0-[expr [expr $table_size - 2] * 8]s $comh_hex]
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append comh_hex "00000000" [checksum8bit $comh_hex] "000000"
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# creating file
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set sys_mem_hex [format %0-[expr 512 * 8]s [concat $comh_hex$verh_hex$projname_hex$boardname_hex$custom_hex]]
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set sys_mem_file [open "mem_init_sys.txt" "w"]
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# writting 32 bits to each line
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for {set i 0} {$i < [string length $sys_mem_hex]} {incr i} {
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if { ($i+1) % 8 == 0} {
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puts $sys_mem_file [string index $sys_mem_hex $i]
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} else {
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puts -nonewline $sys_mem_file [string index $sys_mem_hex $i]
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}
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}
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close $sys_mem_file
|
||||
}
|
||||
|
||||
## Generates a file used for initializing the PR ROM.
|
||||
#
|
||||
# \param[custom_string] - string input
|
||||
#
|
||||
|
||||
proc sysid_gen_pr_init_file {custom_string} {
|
||||
|
||||
set custom_hex [stringtohex $custom_string 64]
|
||||
|
||||
# creating file
|
||||
set pr_mem_file [open "mem_init_pr.txt" "w"]
|
||||
|
||||
# writting 32 bits to each line
|
||||
for {set i 0} {$i < [string length $custom_hex]} {incr i} {
|
||||
if { ($i+1) % 8 == 0} {
|
||||
puts $pr_mem_file [string index $custom_hex $i]
|
||||
} else {
|
||||
puts -nonewline $pr_mem_file [string index $custom_hex $i]
|
||||
}
|
||||
}
|
||||
close $pr_mem_file
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue