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mitx045: Base design now support 2014.2

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Istvan Csomortani 2014-10-09 15:11:28 +03:00
parent edeeafa47d
commit 4f6aa159b8
2 changed files with 4 additions and 8 deletions
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4
projects/common/mitx045/mitx045.xml
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@ -8,10 +8,6 @@
<set param="PCW::USB0::RESET::IO" value="MIO 7" />
<set param="PCW::USB0::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::USB0::RESET::ENABLE" value="1" />
<set param="PCW::QSPI::GRP_FBCLK::ENABLE" value="1" />
<set param="PCW::QSPI::GRP_IO1::ENABLE" value="1" />
<set param="PCW::QSPI::GRP_SS1::ENABLE" value="1" />
<set param="PCW::QSPI::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::WDT::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::PJTAG::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::MIO::MIO[1]::SLEW" value="slow" />

8
projects/common/mitx045/mitx045_system_bd.tcl
View File

@ -31,8 +31,8 @@ set i2s_sdata_in [create_bd_port -dir I i2s_sdata_in]
# instance: sys_ps7
set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.3 sys_ps7]
set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET $ad_hdl_dir/projects/common/mitx045/mitx045.xml ] [get_bd_cells sys_ps7]
set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.4 sys_ps7]
set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET "$ad_hdl_dir/projects/common/mitx045/mitx045.xml" ] $sys_ps7
set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} ] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
@ -50,7 +50,7 @@ set_property -dict [list CONFIG.PCW_USE_DMA2 {1}] $sys_ps7
set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
set_property -dict [list CONFIG.USE_BOARD_FLOW {true} CONFIG.IIC_BOARD_INTERFACE {IIC_MAIN}] $axi_iic_main
set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_concat_intc]
set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc
set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect]
@ -64,7 +64,7 @@ set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.1 axi_hdmi_dma]
set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma