axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters
Group configuration parameters by function, provide human readable labels as well as specify the allowed ranges for each parameter. This prevents accidental misconfiguration and also makes it easier to inspect (or change) the configuration in the Qsys GUI. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
Lars-Peter Clausen
parent
63f280676a
commit
4f009620b5
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@ -45,110 +45,90 @@ add_fileset_file axi_dmac_constr.sdc SDC PATH axi_dmac_constr.sdc
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# parameters
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# parameters
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set group "General Configuration"
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add_parameter ID INTEGER 0
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add_parameter ID INTEGER 0
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set_parameter_property ID DEFAULT_VALUE 0
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set_parameter_property ID DISPLAY_NAME "Core ID"
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set_parameter_property ID DISPLAY_NAME ID
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set_parameter_property ID TYPE INTEGER
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set_parameter_property ID UNITS None
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set_parameter_property ID HDL_PARAMETER true
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set_parameter_property ID HDL_PARAMETER true
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set_parameter_property ID GROUP $group
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add_parameter DMA_DATA_WIDTH_SRC INTEGER 0
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add_parameter DMA_LENGTH_WIDTH INTEGER 24
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set_parameter_property DMA_DATA_WIDTH_SRC DEFAULT_VALUE 64
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set_parameter_property DMA_LENGTH_WIDTH DISPLAY_NAME "DMA Transfer Length Register Width"
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set_parameter_property DMA_DATA_WIDTH_SRC DISPLAY_NAME DMA_DATA_WIDTH_SRC
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set_parameter_property DMA_LENGTH_WIDTH UNITS Bits
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set_parameter_property DMA_DATA_WIDTH_SRC TYPE INTEGER
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set_parameter_property DMA_DATA_WIDTH_SRC UNITS None
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set_parameter_property DMA_DATA_WIDTH_SRC HDL_PARAMETER true
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add_parameter DMA_DATA_WIDTH_DEST INTEGER 0
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set_parameter_property DMA_DATA_WIDTH_DEST DEFAULT_VALUE 64
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set_parameter_property DMA_DATA_WIDTH_DEST DISPLAY_NAME DMA_DATA_WIDTH_DEST
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set_parameter_property DMA_DATA_WIDTH_DEST TYPE INTEGER
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set_parameter_property DMA_DATA_WIDTH_DEST UNITS None
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set_parameter_property DMA_DATA_WIDTH_DEST HDL_PARAMETER true
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add_parameter DMA_LENGTH_WIDTH INTEGER 0
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set_parameter_property DMA_LENGTH_WIDTH DEFAULT_VALUE 24
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set_parameter_property DMA_LENGTH_WIDTH DISPLAY_NAME DMA_LENGTH_WIDTH
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set_parameter_property DMA_LENGTH_WIDTH TYPE INTEGER
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set_parameter_property DMA_LENGTH_WIDTH UNITS None
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set_parameter_property DMA_LENGTH_WIDTH HDL_PARAMETER true
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set_parameter_property DMA_LENGTH_WIDTH HDL_PARAMETER true
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set_parameter_property DMA_LENGTH_WIDTH ALLOWED_RANGES {8:32}
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set_parameter_property DMA_LENGTH_WIDTH GROUP $group
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add_parameter DMA_2D_TRANSFER INTEGER 0
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add_parameter FIFO_SIZE INTEGER 4
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set_parameter_property DMA_2D_TRANSFER DEFAULT_VALUE 1
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set_parameter_property FIFO_SIZE DISPLAY_NAME "FIFO Size (In Bursts)"
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set_parameter_property DMA_2D_TRANSFER DISPLAY_NAME DMA_2D_TRANSFER
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set_parameter_property FIFO_SIZE HDL_PARAMETER true
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set_parameter_property DMA_2D_TRANSFER TYPE INTEGER
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set_parameter_property FIFO_SIZE GROUP $group
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set_parameter_property DMA_2D_TRANSFER UNITS None
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foreach {suffix group} { \
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"SRC" "Source" \
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"DEST" "Destination" \
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} {
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add_display_item "Endpoint Configuration" $group "group"
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add_parameter DMA_TYPE_$suffix INTEGER 0
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set_parameter_property DMA_TYPE_$suffix DISPLAY_NAME "Type"
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set_parameter_property DMA_TYPE_$suffix HDL_PARAMETER true
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set_parameter_property DMA_TYPE_$suffix ALLOWED_RANGES \
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{ "0:Memory-Mapped AXI" "1:Streaming AXI" "2:FIFO Interface" }
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set_parameter_property DMA_TYPE_$suffix GROUP $group
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add_parameter DMA_DATA_WIDTH_$suffix INTEGER 64
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set_parameter_property DMA_DATA_WIDTH_$suffix DISPLAY_NAME "Bus Width"
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set_parameter_property DMA_DATA_WIDTH_$suffix UNITS Bits
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set_parameter_property DMA_DATA_WIDTH_$suffix HDL_PARAMETER true
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set_parameter_property DMA_DATA_WIDTH_$suffix ALLOWED_RANGES {16 32 64 128 256 512 1024}
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set_parameter_property DMA_DATA_WIDTH_$suffix GROUP $group
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add_parameter AXI_SLICE_$suffix INTEGER 0
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set_parameter_property AXI_SLICE_$suffix DISPLAY_NAME "Insert Register Slice"
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set_parameter_property AXI_SLICE_$suffix DISPLAY_HINT boolean
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set_parameter_property AXI_SLICE_$suffix HDL_PARAMETER true
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set_parameter_property AXI_SLICE_$suffix GROUP $group
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}
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# FIFO interface
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set_parameter_property DMA_TYPE_SRC DEFAULT_VALUE 2
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set group "Features"
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add_parameter CYCLIC INTEGER 1
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set_parameter_property CYCLIC DISPLAY_NAME "Cyclic Transfer Support"
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set_parameter_property CYCLIC DISPLAY_HINT boolean
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set_parameter_property CYCLIC HDL_PARAMETER true
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set_parameter_property CYCLIC GROUP $group
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add_parameter DMA_2D_TRANSFER INTEGER 1
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set_parameter_property DMA_2D_TRANSFER DISPLAY_NAME "2D Transfer Support"
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set_parameter_property DMA_2D_TRANSFER DISPLAY_HINT boolean
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set_parameter_property DMA_2D_TRANSFER HDL_PARAMETER true
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set_parameter_property DMA_2D_TRANSFER HDL_PARAMETER true
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set_parameter_property DMA_2D_TRANSFER GROUP $group
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add_parameter ASYNC_CLK_REQ_SRC INTEGER 0
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set_parameter_property ASYNC_CLK_REQ_SRC DEFAULT_VALUE 1
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set_parameter_property ASYNC_CLK_REQ_SRC DISPLAY_NAME ASYNC_CLK_REQ_SRC
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set_parameter_property ASYNC_CLK_REQ_SRC TYPE INTEGER
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set_parameter_property ASYNC_CLK_REQ_SRC UNITS None
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set_parameter_property ASYNC_CLK_REQ_SRC HDL_PARAMETER true
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add_parameter ASYNC_CLK_SRC_DEST INTEGER 0
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set_parameter_property ASYNC_CLK_SRC_DEST DEFAULT_VALUE 1
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set_parameter_property ASYNC_CLK_SRC_DEST DISPLAY_NAME ASYNC_CLK_SRC_DEST
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set_parameter_property ASYNC_CLK_SRC_DEST TYPE INTEGER
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set_parameter_property ASYNC_CLK_SRC_DEST UNITS None
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set_parameter_property ASYNC_CLK_SRC_DEST HDL_PARAMETER true
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add_parameter ASYNC_CLK_DEST_REQ INTEGER 0
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set_parameter_property ASYNC_CLK_DEST_REQ DEFAULT_VALUE 1
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set_parameter_property ASYNC_CLK_DEST_REQ DISPLAY_NAME ASYNC_CLK_DEST_REQ
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set_parameter_property ASYNC_CLK_DEST_REQ TYPE INTEGER
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set_parameter_property ASYNC_CLK_DEST_REQ UNITS None
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set_parameter_property ASYNC_CLK_DEST_REQ HDL_PARAMETER true
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add_parameter AXI_SLICE_DEST INTEGER 0
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set_parameter_property AXI_SLICE_DEST DEFAULT_VALUE 0
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set_parameter_property AXI_SLICE_DEST DISPLAY_NAME AXI_SLICE_DEST
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set_parameter_property AXI_SLICE_DEST TYPE INTEGER
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set_parameter_property AXI_SLICE_DEST UNITS None
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set_parameter_property AXI_SLICE_DEST HDL_PARAMETER true
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add_parameter AXI_SLICE_SRC INTEGER 0
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set_parameter_property AXI_SLICE_SRC DEFAULT_VALUE 0
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set_parameter_property AXI_SLICE_SRC DISPLAY_NAME AXI_SLICE_SRC
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set_parameter_property AXI_SLICE_SRC TYPE INTEGER
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set_parameter_property AXI_SLICE_SRC UNITS None
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set_parameter_property AXI_SLICE_SRC HDL_PARAMETER true
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add_parameter SYNC_TRANSFER_START INTEGER 0
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add_parameter SYNC_TRANSFER_START INTEGER 0
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set_parameter_property SYNC_TRANSFER_START DEFAULT_VALUE 0
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set_parameter_property SYNC_TRANSFER_START DISPLAY_NAME "Transfer Start Synchronization Support"
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set_parameter_property SYNC_TRANSFER_START DISPLAY_NAME SYNC_TRANSFER_START
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set_parameter_property SYNC_TRANSFER_START DISPLAY_HINT boolean
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set_parameter_property SYNC_TRANSFER_START TYPE INTEGER
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set_parameter_property SYNC_TRANSFER_START UNITS None
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set_parameter_property SYNC_TRANSFER_START HDL_PARAMETER true
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set_parameter_property SYNC_TRANSFER_START HDL_PARAMETER true
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set_parameter_property SYNC_TRANSFER_START GROUP $group
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add_parameter CYCLIC INTEGER 0
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set group "Clock Domain Configuration"
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set_parameter_property CYCLIC DEFAULT_VALUE 1
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set_parameter_property CYCLIC DISPLAY_NAME CYCLIC
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set_parameter_property CYCLIC TYPE INTEGER
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set_parameter_property CYCLIC UNITS None
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set_parameter_property CYCLIC HDL_PARAMETER true
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add_parameter DMA_TYPE_DEST INTEGER 0
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foreach {p name} { \
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set_parameter_property DMA_TYPE_DEST DEFAULT_VALUE 0
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ASYNC_CLK_REQ_SRC "Request and Source" \
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set_parameter_property DMA_TYPE_DEST DISPLAY_NAME DMA_TYPE_DEST
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ASYNC_CLK_SRC_DEST "Source and Destination" \
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set_parameter_property DMA_TYPE_DEST TYPE INTEGER
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ASYNC_CLK_DEST_REQ "Destination and Request" \
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set_parameter_property DMA_TYPE_DEST UNITS None
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} {
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set_parameter_property DMA_TYPE_DEST HDL_PARAMETER true
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add_parameter DMA_TYPE_SRC INTEGER 0
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add_parameter $p INTEGER 1
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set_parameter_property DMA_TYPE_SRC DEFAULT_VALUE 2
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set_parameter_property $p DISPLAY_NAME [concat $name "Clock Asynchronous"]
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set_parameter_property DMA_TYPE_SRC DISPLAY_NAME DMA_TYPE_SRC
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set_parameter_property $p DISPLAY_HINT boolean
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set_parameter_property DMA_TYPE_SRC TYPE INTEGER
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set_parameter_property $p HDL_PARAMETER true
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set_parameter_property DMA_TYPE_SRC UNITS None
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set_parameter_property $p GROUP $group
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set_parameter_property DMA_TYPE_SRC HDL_PARAMETER true
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}
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add_parameter FIFO_SIZE INTEGER 0 "In bursts"
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set_parameter_property FIFO_SIZE DEFAULT_VALUE 4
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set_parameter_property FIFO_SIZE DISPLAY_NAME FIFO_SIZE
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set_parameter_property FIFO_SIZE TYPE INTEGER
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set_parameter_property FIFO_SIZE UNITS None
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set_parameter_property FIFO_SIZE HDL_PARAMETER true
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# axi4 slave
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# axi4 slave
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