fmcomms2_pr: zc706: Fix ddr and fixed_io signal names
The toplevel input/output signal names are lower case, but the signals connected to the system_wrapper are upper case. Since verilog is case sensitive this leaves the toplevel input/output signals unconnected. Fix this by using lower case names everywhere. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
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@ -235,28 +235,28 @@ module system_top (
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system_wrapper i_system_wrapper (
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.ddr_addr (DDR_addr),
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.ddr_ba (DDR_ba),
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.ddr_cas_n (DDR_cas_n),
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.ddr_ck_n (DDR_ck_n),
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.ddr_ck_p (DDR_ck_p),
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.ddr_cke (DDR_cke),
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.ddr_cs_n (DDR_cs_n),
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.ddr_dm (DDR_dm),
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.ddr_dq (DDR_dq),
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.ddr_dqs_n (DDR_dqs_n),
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.ddr_dqs_p (DDR_dqs_p),
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.ddr_odt (DDR_odt),
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.ddr_ras_n (DDR_ras_n),
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.ddr_reset_n (DDR_reset_n),
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.ddr_we_n (DDR_we_n),
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.fixed_io_ddr_vrn (FIXED_IO_ddr_vrn),
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.fixed_io_ddr_vrp (FIXED_IO_ddr_vrp),
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.fixed_io_mio (FIXED_IO_mio),
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.fixed_io_ps_clk (FIXED_IO_ps_clk),
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.fixed_io_ps_porb (FIXED_IO_ps_porb),
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.fixed_io_ps_srstb (FIXED_IO_ps_srstb),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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