fmcadc4: update adcfifo/dacfifo
parent
51e35e081f
commit
4ec1204767
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@ -1,6 +1,10 @@
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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set adc_fifo_name axi_ad9680_fifo
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set adc_data_width 256
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set adc_dma_data_width 64
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# fmcadc4
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# fmcadc4
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# adc peripherals
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# adc peripherals
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@ -30,6 +34,8 @@ ad_ip_parameter axi_ad9680_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC 64
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC 64
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width
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ad_ip_instance util_cpack2 axi_ad9680_cpack { \
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ad_ip_instance util_cpack2 axi_ad9680_cpack { \
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NUM_OF_CHANNELS 4 \
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NUM_OF_CHANNELS 4 \
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SAMPLES_PER_CHANNEL 4 \
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SAMPLES_PER_CHANNEL 4 \
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@ -1,8 +1,5 @@
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set adc_fifo_name axi_ad9680_fifo
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set adc_fifo_address_width 18
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set adc_fifo_address_width 18
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set adc_data_width 256
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set adc_dma_data_width 64
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl
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