daq3: Update IP instantiations
Istvan Csomortani
parent
1ae357ce10
commit
4eaa43f8e1
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@ -1,68 +1,68 @@
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# dac peripherals
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set axi_ad9152_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9152_xcvr]
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set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9152_xcvr
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set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9152_xcvr
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set_property -dict [list CONFIG.TX_OR_RX_N {1}] $axi_ad9152_xcvr
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ad_ip_instance axi_adxcvr axi_ad9152_xcvr
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ad_ip_parameter axi_ad9152_xcvr CONFIG.NUM_OF_LANES 4
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ad_ip_parameter axi_ad9152_xcvr CONFIG.QPLL_ENABLE 1
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ad_ip_parameter axi_ad9152_xcvr CONFIG.TX_OR_RX_N 1
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set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9152_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9152_jesd
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set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9152_jesd
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ad_ip_instance jesd204 axi_ad9152_jesd
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ad_ip_parameter axi_ad9152_jesd CONFIG.C_NODE_IS_TRANSMIT 1
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ad_ip_parameter axi_ad9152_jesd CONFIG.C_LANES 4
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set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core]
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ad_ip_instance axi_ad9152 axi_ad9152_core
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set axi_ad9152_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 axi_ad9152_upack]
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9152_upack
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9152_upack
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ad_ip_instance util_upack axi_ad9152_upack
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ad_ip_parameter axi_ad9152_upack CONFIG.CHANNEL_DATA_WIDTH 64
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ad_ip_parameter axi_ad9152_upack CONFIG.NUM_OF_CHANNELS 2
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set axi_ad9152_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9152_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9152_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9152_dma
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set_property -dict [list CONFIG.ID {1}] $axi_ad9152_dma
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set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9152_dma
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set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9152_dma
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set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9152_dma
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set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9152_dma
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set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9152_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9152_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9152_dma
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ad_ip_instance axi_dmac axi_ad9152_dma
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ad_ip_parameter axi_ad9152_dma CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter axi_ad9152_dma CONFIG.DMA_TYPE_DEST 1
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ad_ip_parameter axi_ad9152_dma CONFIG.ID 1
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ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_ad9152_dma CONFIG.DMA_LENGTH_WIDTH 24
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ad_ip_parameter axi_ad9152_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad9152_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad9152_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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ad_ip_parameter axi_ad9152_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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# adc peripherals
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set axi_ad9680_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9680_xcvr]
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set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9680_xcvr
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set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9680_xcvr
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set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9680_xcvr
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ad_ip_instance axi_adxcvr axi_ad9680_xcvr
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ad_ip_parameter axi_ad9680_xcvr CONFIG.NUM_OF_LANES 4
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ad_ip_parameter axi_ad9680_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_ad9680_xcvr CONFIG.TX_OR_RX_N 0
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set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
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set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd
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ad_ip_instance jesd204 axi_ad9680_jesd
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ad_ip_parameter axi_ad9680_jesd CONFIG.C_NODE_IS_TRANSMIT 0
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ad_ip_parameter axi_ad9680_jesd CONFIG.C_LANES 4
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set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
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ad_ip_instance axi_ad9680 axi_ad9680_core
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set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack]
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack
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ad_ip_instance util_cpack axi_ad9680_cpack
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ad_ip_parameter axi_ad9680_cpack CONFIG.CHANNEL_DATA_WIDTH 64
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ad_ip_parameter axi_ad9680_cpack CONFIG.NUM_OF_CHANNELS 2
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set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9680_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.ID {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9680_dma
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set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma
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set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
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ad_ip_instance axi_dmac axi_ad9680_dma
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad9680_dma CONFIG.ID 0
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ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_ad9680_dma CONFIG.SYNC_TRANSFER_START 1
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_LENGTH_WIDTH 24
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad9680_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC 64
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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# shared transceiver core
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set util_daq3_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_daq3_xcvr]
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_daq3_xcvr
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq3_xcvr
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ad_ip_instance util_adxcvr util_daq3_xcvr
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ad_ip_parameter util_daq3_xcvr CONFIG.RX_NUM_OF_LANES 4
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ad_ip_parameter util_daq3_xcvr CONFIG.TX_NUM_OF_LANES 4
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ad_connect sys_cpu_resetn util_daq3_xcvr/up_rstn
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ad_connect sys_cpu_clk util_daq3_xcvr/up_clk
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@ -14,7 +14,7 @@ source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
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source ../common/daq3_bd.tcl
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set_property -dict [list CONFIG.XCVR_TYPE {1}] $util_daq3_xcvr
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set_property -dict [list CONFIG.QPLL_FBDIV {20}] $util_daq3_xcvr
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set_property -dict [list CONFIG.QPLL_REFCLK_DIV {1}] $util_daq3_xcvr
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ad_ip_parameter util_daq3_xcvr CONFIG.XCVR_TYPE 1
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ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV 20
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ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_REFCLK_DIV 1
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