From 4ea6b0d6d80487e0d73e586c487e2a13f9f2c552 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Mon, 10 Jul 2017 13:38:31 +0100 Subject: [PATCH] jesd204: Update constraints for tx register map In some cases, the 'core_ilas_config_data' registers will be infered as FDRE, instead of FDSE. Therefor a max delay definition, which are using the S pin as its endpoint, it can become invalid, nonexistent. Generalize the path, using the register itself as endpoint. --- library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc index da4425cae..40eefb9ea 100644 --- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc +++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc @@ -113,12 +113,7 @@ set_max_delay -datapath_only \ set_max_delay -datapath_only \ -from [get_pins {i_up_tx/up_cfg_ilas_data_*_reg*/C}] \ - -to [get_pins {i_up_tx/*core_ilas_config_data_reg*/D}] \ - [get_property -min PERIOD $core_clk] - -set_max_delay -datapath_only \ - -from [get_pins {i_up_tx/up_cfg_ilas_data_*_reg*/C}] \ - -to [get_pins {i_up_tx/*core_ilas_config_data_reg*/S}] \ + -to [get_cells {i_up_tx/*core_ilas_config_data_reg*}] \ [get_property -min PERIOD $core_clk] set_max_delay -datapath_only \