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jesd204: Update constraints for tx register map 

In some cases, the 'core_ilas_config_data' registers will be infered as
FDRE, instead of FDSE. Therefor a max delay definition, which are using
the S pin as its endpoint, it can become invalid, nonexistent.
Generalize the path, using the register itself as endpoint.
main
Istvan Csomortani 2017-07-10 13:38:31 +01:00
parent 98cf18dd51
commit 4ea6b0d6d8
1 changed files with 1 additions and 6 deletions
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7
library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc
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@ -113,12 +113,7 @@ set_max_delay -datapath_only \
set_max_delay -datapath_only \
-from [get_pins {i_up_tx/up_cfg_ilas_data_*_reg*/C}] \
-to [get_pins {i_up_tx/*core_ilas_config_data_reg*/D}] \
[get_property -min PERIOD $core_clk]
set_max_delay -datapath_only \
-from [get_pins {i_up_tx/up_cfg_ilas_data_*_reg*/C}] \
-to [get_pins {i_up_tx/*core_ilas_config_data_reg*/S}] \
-to [get_cells {i_up_tx/*core_ilas_config_data_reg*}] \
[get_property -min PERIOD $core_clk]
set_max_delay -datapath_only \