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xcvr: remove signal tap

main
Rejeesh Kutty 2015-07-16 08:09:06 -04:00
parent 9f7fff2d2f
commit 4e99a2cb01
4 changed files with 4 additions and 121 deletions
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25
library/axi_jesd_xcvr/axi_jesd_xcvr.v
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@ -82,20 +82,12 @@ module axi_jesd_xcvr (
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready,
// signal tap interface
stp_clk,
stp_data,
stp_trigger);
s_axi_rready);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_NUM_OF_TX_LANES = 4;
parameter PCORE_NUM_OF_RX_LANES = 4;
parameter PCORE_ST_DATA_WIDTH = 32;
parameter PCORE_ST_TRIGGER_WIDTH = 4;
// receive interface
@ -142,12 +134,6 @@ module axi_jesd_xcvr (
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// signal tap interface
output stp_clk;
output [(PCORE_ST_DATA_WIDTH-1):0] stp_data;
output [(PCORE_ST_TRIGGER_WIDTH-1):0] stp_trigger;
// internal signals
wire up_rstn;
@ -221,9 +207,7 @@ module axi_jesd_xcvr (
sys_xcvr #(
.PCORE_NUM_OF_TX_LANES (PCORE_NUM_OF_TX_LANES),
.PCORE_NUM_OF_RX_LANES (PCORE_NUM_OF_RX_LANES),
.PCORE_ST_DATA_WIDTH (PCORE_ST_DATA_WIDTH),
.PCORE_ST_TRIGGER_WIDTH (PCORE_ST_TRIGGER_WIDTH))
.PCORE_NUM_OF_RX_LANES (PCORE_NUM_OF_RX_LANES))
i_sys_xcvr (
.up_clk (up_clk),
.up_rstn (up_rstn),
@ -246,10 +230,7 @@ module axi_jesd_xcvr (
.tx_ip_sync (tx_ip_sync_s),
.tx_ip_data (tx_ip_data_s),
.tx_ready (tx_ready_s),
.tx_int (),
.stp_clk (stp_clk),
.stp_data (stp_data),
.stp_trigger (stp_trigger));
.tx_int ());
// processor

25
library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
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@ -50,20 +50,6 @@ set_parameter_property PCORE_NUM_OF_RX_LANES TYPE INTEGER
set_parameter_property PCORE_NUM_OF_RX_LANES UNITS None
set_parameter_property PCORE_NUM_OF_RX_LANES HDL_PARAMETER true
add_parameter PCORE_ST_DATA_WIDTH INTEGER 0
set_parameter_property PCORE_ST_DATA_WIDTH DEFAULT_VALUE 32
set_parameter_property PCORE_ST_DATA_WIDTH DISPLAY_NAME PCORE_ST_DATA_WIDTH
set_parameter_property PCORE_ST_DATA_WIDTH TYPE INTEGER
set_parameter_property PCORE_ST_DATA_WIDTH UNITS None
set_parameter_property PCORE_ST_DATA_WIDTH HDL_PARAMETER true
add_parameter PCORE_ST_TRIGGER_WIDTH INTEGER 0
set_parameter_property PCORE_ST_TRIGGER_WIDTH DEFAULT_VALUE 32
set_parameter_property PCORE_ST_TRIGGER_WIDTH DISPLAY_NAME PCORE_ST_TRIGGER_WIDTH
set_parameter_property PCORE_ST_TRIGGER_WIDTH TYPE INTEGER
set_parameter_property PCORE_ST_TRIGGER_WIDTH UNITS None
set_parameter_property PCORE_ST_TRIGGER_WIDTH HDL_PARAMETER true
# axi4 slave
add_interface s_axi_clock clock end
@ -115,14 +101,3 @@ ad_alt_intf signal tx_ext_sysref_out output 1
ad_alt_intf signal tx_sync input 1
ad_alt_intf signal tx_data input PCORE_NUM_OF_TX_LANES*32 data
# signal tap interface
ad_alt_intf clock stp_clk output 1
add_interface if_stp conduit source
add_interface_port if_stp stp_data acq_data_in output PCORE_ST_DATA_WIDTH
add_interface_port if_stp stp_trigger acq_trigger_in output PCORE_ST_TRIGGER_WIDTH
set_interface_property if_stp associatedClock if_stp_clk

48
projects/fmcjesdadc1/a5gt/system_bd.qsys
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@ -346,14 +346,6 @@
type = "boolean";
}
}
element sys_signaltap
{
datum _sortIndex
{
value = "22";
type = "int";
}
}
element sys_spi
{
datum _sortIndex
@ -690,8 +682,6 @@
<parameter name="PCORE_ID" value="0" />
<parameter name="PCORE_NUM_OF_RX_LANES" value="4" />
<parameter name="PCORE_NUM_OF_TX_LANES" value="4" />
<parameter name="PCORE_ST_DATA_WIDTH" value="182" />
<parameter name="PCORE_ST_TRIGGER_WIDTH" value="2" />
</module>
<module name="sys_clk" kind="clock_source" version="15.0" enabled="1">
<parameter name="clockFrequency" value="100000000" />
@ -1574,28 +1564,6 @@
<parameter name="gui_switchover_mode">Automatic Switchover</parameter>
<parameter name="gui_use_locked" value="true" />
</module>
<module
name="sys_signaltap"
kind="altera_signaltap_ii_logic_analyzer"
version="15.0"
enabled="1">
<parameter name="device_family" value="Arria V" />
<parameter name="gui_num_segments" value="2" />
<parameter name="gui_ram_type" value="AUTO" />
<parameter name="gui_sq" value="Continuous" />
<parameter name="gui_trigger_out_enabled" value="false" />
<parameter name="gui_use_segmented" value="false" />
<parameter name="sld_data_bits" value="182" />
<parameter name="sld_enable_advanced_trigger" value="0" />
<parameter name="sld_node_crc_bits" value="32" />
<parameter name="sld_node_info" value="806383104" />
<parameter name="sld_sample_depth" value="128" />
<parameter name="sld_storage_qualifier_gap_record" value="0" />
<parameter name="sld_trigger_bits" value="2" />
<parameter name="sld_trigger_in_enabled" value="0" />
<parameter name="sld_trigger_level" value="1" />
<parameter name="sld_trigger_level_pipeline" value="1" />
</module>
<module name="sys_spi" kind="altera_avalon_spi" version="15.0" enabled="1">
<parameter name="avalonSpec" value="2.0" />
<parameter name="clockPhase" value="0" />
@ -2020,11 +1988,6 @@
version="15.0"
start="axi_jesd_xcvr.if_rx_clk"
end="axi_ad9250_1.if_rx_clk" />
<connection
kind="clock"
version="15.0"
start="axi_jesd_xcvr.if_stp_clk"
end="sys_signaltap.acq_clk" />
<connection
kind="conduit"
version="15.0"
@ -2278,17 +2241,6 @@
<parameter name="startPortLSB" value="0" />
<parameter name="width" value="0" />
</connection>
<connection
kind="conduit"
version="15.0"
start="sys_signaltap.tap"
end="axi_jesd_xcvr.if_stp">
<parameter name="endPort" value="" />
<parameter name="endPortLSB" value="0" />
<parameter name="startPort" value="" />
<parameter name="startPortLSB" value="0" />
<parameter name="width" value="0" />
</connection>
<connection
kind="interrupt"
version="15.0"

27
projects/fmcjesdadc1/common/sys_xcvr.v
View File

@ -69,18 +69,12 @@ module sys_xcvr (
tx_ip_sync,
tx_ip_data,
tx_ready,
tx_int,
stp_clk,
stp_data,
stp_trigger);
tx_int);
// parameters are not used--
parameter PCORE_NUM_OF_TX_LANES = 4;
parameter PCORE_NUM_OF_RX_LANES = 4;
parameter PCORE_ST_DATA_WIDTH = 32;
parameter PCORE_ST_TRIGGER_WIDTH = 4;
// io
@ -111,10 +105,6 @@ module sys_xcvr (
output [ 3:0] tx_ready;
output tx_int;
output stp_clk;
output [181:0] stp_data;
output [ 1:0] stp_trigger;
// internal signals
wire [ 3:0] rx_analogreset;
@ -135,21 +125,6 @@ module sys_xcvr (
wire [ 15:0] rx_pcs_kchar;
wire [127:0] rx_pcs_data;
// signal tap
assign stp_clk = rx_clk;
assign stp_data[181:181] = rx_sysref;
assign stp_data[180:180] = rx_ip_sync;
assign stp_data[179:176] = rx_pcs_valid;
assign stp_data[175:160] = rx_pcs_disperr;
assign stp_data[159:144] = rx_pcs_errdetect;
assign stp_data[143:128] = rx_pcs_kchar;
assign stp_data[127: 0] = rx_pcs_data;
assign stp_trigger[1] = rx_sysref;
assign stp_trigger[0] = rx_ip_sync;
// instantiations
sys_xcvr_rstcntrl_rx_pll i_rstcntrl_rx_pll (