From 4e644e4e74bf2c2816fe815c51d49757e4630fb8 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Fri, 21 Jan 2022 09:00:28 +0000 Subject: [PATCH] jesd204/ad_ip_jesd204_tpl_dac: External sync refactor - Expose EXT_SYNC parameter to sw - Add external manual sync request - Add rst to interface --- library/common/util_ext_sync.v | 65 +++++++++++++++++++ .../jesd204/ad_ip_jesd204_tpl_dac/Makefile | 1 + .../ad_ip_jesd204_tpl_dac.v | 12 +++- .../ad_ip_jesd204_tpl_dac_core.v | 46 +++++++------ .../ad_ip_jesd204_tpl_dac_ip.tcl | 5 ++ .../ad_ip_jesd204_tpl_dac_regmap.v | 10 ++- 6 files changed, 112 insertions(+), 27 deletions(-) create mode 100644 library/common/util_ext_sync.v diff --git a/library/common/util_ext_sync.v b/library/common/util_ext_sync.v new file mode 100644 index 000000000..e68736872 --- /dev/null +++ b/library/common/util_ext_sync.v @@ -0,0 +1,65 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// +// Each core or library found in this collection may have its own licensing terms. +// The user should keep this in in mind while exploring these cores. +// +// Redistribution and use in source and binary forms, +// with or without modification of this file, are permitted under the terms of either +// (at the option of the user): +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory, or at: +// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// +// OR +// +// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: +// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_ext_sync #( + parameter ENABLED = 1 +) ( + input clk, + + input ext_sync_arm, + input ext_sync_disarm, + + input sync_in, + + output reg sync_armed = 1'b0 + +); + + reg sync_in_d1 = 1'b0; + reg sync_in_d2 = 1'b0; + reg ext_sync_arm_d1 = 1'b0; + reg ext_sync_disarm_d1 = 1'b0; + + // External sync + always @(posedge clk) begin + ext_sync_arm_d1 <= ext_sync_arm; + ext_sync_disarm_d1 <= ext_sync_disarm; + + sync_in_d1 <= sync_in ; + sync_in_d2 <= sync_in_d1; + + if (ENABLED == 1'b0) begin + sync_armed <= 1'b0; + end else if (~ext_sync_disarm_d1 & ext_sync_disarm) begin + sync_armed <= 1'b0; + end else if (~ext_sync_arm_d1 & ext_sync_arm) begin + sync_armed <= 1'b1; + end else if (~sync_in_d2 & sync_in_d1) begin + sync_armed <= 1'b0; + end + end + +endmodule + diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/Makefile b/library/jesd204/ad_ip_jesd204_tpl_dac/Makefile index 676fdda32..a400a20fb 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/Makefile +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/Makefile @@ -23,6 +23,7 @@ GENERIC_DEPS += ../../common/up_dac_channel.v GENERIC_DEPS += ../../common/up_dac_common.v GENERIC_DEPS += ../../common/up_xfer_cntrl.v GENERIC_DEPS += ../../common/up_xfer_status.v +GENERIC_DEPS += ../../common/util_ext_sync.v GENERIC_DEPS += ../ad_ip_jesd204_tpl_common/up_tpl_common.v GENERIC_DEPS += ad_ip_jesd204_tpl_dac.v GENERIC_DEPS += ad_ip_jesd204_tpl_dac_channel.v diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v index 10da61760..dd29f0628 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v @@ -60,9 +60,13 @@ module ad_ip_jesd204_tpl_dac #( input [DMA_BITS_PER_SAMPLE * OCTETS_PER_BEAT * 8 * NUM_LANES / BITS_PER_SAMPLE-1:0] dac_ddata, input dac_dunf, + output dac_rst, + // external sync, should be on the link_clk clock domain input dac_sync_in, + output dac_sync_manual_req_out, + input dac_sync_manual_req_in, // axi interface @@ -138,7 +142,8 @@ module ad_ip_jesd204_tpl_dac #( .NUM_CHANNELS (NUM_CHANNELS), .DATA_PATH_WIDTH (DATA_PATH_WIDTH), .PADDING_TO_MSB_LSB_N (PADDING_TO_MSB_LSB_N), - .NUM_PROFILES(1) + .NUM_PROFILES(1), + .EXT_SYNC (EXT_SYNC) ) i_regmap ( .s_axi_aclk (s_axi_aclk), .s_axi_aresetn (s_axi_aresetn), @@ -169,6 +174,8 @@ module ad_ip_jesd204_tpl_dac #( .dac_sync (dac_sync), .dac_ext_sync_arm (dac_ext_sync_arm), + .dac_ext_sync_disarm (dac_ext_sync_disarm), + .dac_ext_sync_manual_req (dac_sync_manual_req_out), .dac_sync_in_status (dac_sync_in_status), .dac_dds_format (dac_dds_format), @@ -227,11 +234,14 @@ module ad_ip_jesd204_tpl_dac #( .dac_valid (dac_valid), .dac_ddata (dac_ddata_cr), + .dac_rst (dac_rst), .dac_sync (dac_sync), .dac_ext_sync_arm (dac_ext_sync_arm), + .dac_ext_sync_disarm (dac_ext_sync_disarm), .dac_sync_in_status (dac_sync_in_status), .dac_sync_in (dac_sync_in), + .dac_sync_manual_req (dac_sync_manual_req_in), .dac_dds_format (dac_dds_format), .dac_dds_scale_0 (dac_dds_scale_0_s), diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v index 910176085..eeeeaae97 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v @@ -50,13 +50,16 @@ module ad_ip_jesd204_tpl_dac_core #( // dma interface output [NUM_CHANNELS-1:0] dac_valid, input [LINK_DATA_WIDTH-1:0] dac_ddata, + output dac_rst, // Configuration interface input dac_sync, input dac_ext_sync_arm, + input dac_ext_sync_disarm, input dac_sync_in, + input dac_sync_manual_req, output dac_sync_in_status, @@ -93,32 +96,23 @@ module ad_ip_jesd204_tpl_dac_core #( wire [DAC_CDW-1:0] pn7_data; wire [DAC_CDW-1:0] pn15_data; - reg dac_sync_in_d1 ='d0; - reg dac_sync_in_d2 ='d0; - reg dac_sync_in_armed ='d0; - reg dac_ext_sync_arm_d1 = 'd0; + wire [LINK_DATA_WIDTH-1:0] dac_ddata_int; assign link_valid = 1'b1; - assign dac_sync_in_status = dac_sync_in_armed; + assign dac_sync_in_status = dac_sync_armed; - // External sync - always @(posedge clk) begin - dac_ext_sync_arm_d1 <= dac_ext_sync_arm; - - dac_sync_in_d1 <= dac_sync_in; - dac_sync_in_d2 <= dac_sync_in_d1; - - if (EXT_SYNC == 1'b0) begin - dac_sync_in_armed <= 1'b0; - end else if (~dac_ext_sync_arm_d1 & dac_ext_sync_arm) begin - dac_sync_in_armed <= ~dac_sync_in_armed; - end else if (~dac_sync_in_d2 & dac_sync_in_d1) begin - dac_sync_in_armed <= 1'b0; - end - end + util_ext_sync #( + .ENABLED (EXT_SYNC) + ) i_util_ext_sync ( + .clk (clk), + .ext_sync_arm (dac_ext_sync_arm), + .ext_sync_disarm (dac_ext_sync_disarm), + .sync_in (dac_sync_in | dac_sync_manual_req), + .sync_armed (dac_sync_armed) + ); // Sync either from external or software source - assign dac_sync_int = dac_sync_in_armed | dac_sync; + assign dac_sync_int = dac_sync_armed | dac_sync; // device interface @@ -150,7 +144,11 @@ module ad_ip_jesd204_tpl_dac_core #( // dac valid - assign dac_valid = {NUM_CHANNELS{~dac_sync_int}}; + assign dac_valid = {NUM_CHANNELS{~dac_sync_armed}}; + assign dac_rst = dac_sync_armed; + + // Gate input data + assign dac_ddata_int = dac_sync_armed ? {LINK_DATA_WIDTH{1'b0}} : dac_ddata; generate genvar i; @@ -171,13 +169,13 @@ module ad_ip_jesd204_tpl_dac_core #( .EN_REG (1) ) channel_mux ( .clk (clk), - .data_in (dac_ddata), + .data_in (dac_ddata_int), .ch_sel (dac_src_chan_sel[8*i+:8]), .data_out (dac_ddata_muxed[DAC_CDW*i+:DAC_CDW]) ); end else begin - assign dac_ddata_muxed[DAC_CDW*i+:DAC_CDW] = dac_ddata[DAC_CDW*i+:DAC_CDW]; + assign dac_ddata_muxed[DAC_CDW*i+:DAC_CDW] = dac_ddata_int[DAC_CDW*i+:DAC_CDW]; end ad_ip_jesd204_tpl_dac_channel #( diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl index 5ce3660a2..d41cc36aa 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl @@ -44,6 +44,7 @@ adi_ip_files ad_ip_jesd204_tpl_dac [list \ "$ad_hdl_dir/library/common/up_clock_mon.v" \ "$ad_hdl_dir/library/common/up_dac_common.v" \ "$ad_hdl_dir/library/common/up_dac_channel.v" \ + "$ad_hdl_dir/library/common/util_ext_sync.v" \ "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ @@ -80,6 +81,10 @@ adi_add_bus "link" "master" \ ] adi_add_bus_clock "link_clk" "link" +adi_set_ports_dependency "dac_sync_in" "EXT_SYNC == 1" +adi_set_ports_dependency "dac_sync_manual_req_out" "EXT_SYNC == 1" +adi_set_ports_dependency "dac_sync_manual_req_in" "EXT_SYNC == 1" + set_property -dict [list \ "value_validation_type" "pairs" \ "value_validation_pairs" {"Polynominal" "0" "CORDIC" "1"} \ diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v index 5b3bde5c6..5888f01aa 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v @@ -35,7 +35,8 @@ module ad_ip_jesd204_tpl_dac_regmap #( parameter NUM_CHANNELS = 2, parameter DATA_PATH_WIDTH = 16, parameter PADDING_TO_MSB_LSB_N = 0, - parameter NUM_PROFILES = 1 // Number of supported JESD profiles + parameter NUM_PROFILES = 1, // Number of supported JESD profiles + parameter EXT_SYNC = 0 ) ( input s_axi_aclk, input s_axi_aresetn, @@ -70,6 +71,8 @@ module ad_ip_jesd204_tpl_dac_regmap #( output dac_sync, output dac_ext_sync_arm, + output dac_ext_sync_disarm, + output dac_ext_sync_manual_req, input dac_sync_in_status, @@ -190,7 +193,8 @@ module ad_ip_jesd204_tpl_dac_regmap #( // dac common processor interface // - localparam CONFIG = (PADDING_TO_MSB_LSB_N << 11) | + localparam CONFIG = (EXT_SYNC << 12) | + (PADDING_TO_MSB_LSB_N << 11) | (XBAR_ENABLE << 10) | (DATAPATH_DISABLE << 6) | (IQCORRECTION_DISABLE << 0); @@ -212,6 +216,8 @@ module ad_ip_jesd204_tpl_dac_regmap #( .dac_rst (dac_rst), .dac_sync (dac_sync), .dac_ext_sync_arm (dac_ext_sync_arm), + .dac_ext_sync_disarm (dac_ext_sync_disarm), + .dac_ext_sync_manual_req (dac_ext_sync_manual_req), .dac_sync_in_status (dac_sync_in_status), .dac_frame (), .dac_clksel (),