From 4e3e623530bb6183d5148478593e2d4e2dd03469 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Wed, 23 Nov 2016 14:02:59 -0500 Subject: [PATCH] pzsdr2/ccpci- updates --- projects/pzsdr2/ccpci_lvds/system_constr.xdc | 36 --- projects/pzsdr2/ccpci_lvds/system_top.v | 243 +++++++------------ projects/pzsdr2/common/ccpci_bd.tcl | 7 + projects/pzsdr2/common/ccpci_constr.xdc | 6 +- 4 files changed, 93 insertions(+), 199 deletions(-) delete mode 100644 projects/pzsdr2/ccpci_lvds/system_constr.xdc diff --git a/projects/pzsdr2/ccpci_lvds/system_constr.xdc b/projects/pzsdr2/ccpci_lvds/system_constr.xdc deleted file mode 100644 index bfc2f8efd..000000000 --- a/projects/pzsdr2/ccpci_lvds/system_constr.xdc +++ /dev/null @@ -1,36 +0,0 @@ - -# constraints -# reference-only & not-effective -# (axi_pcie_x0y0.xdc) - -set_property -dict {PACKAGE_PIN U6 } [get_ports pcie_ref_clk_p] ; ## MGTREFCLK1P_112 (JX3.2) (P2.A13) -set_property -dict {PACKAGE_PIN U5 } [get_ports pcie_ref_clk_n] ; ## MGTREFCLK1N_112 (JX3.4) (P2.A14) -set_property -dict {PACKAGE_PIN T4 } [get_ports pcie_data_rx_p[0]] ; ## MGTXRXP3_112 (JX1.97) (P2.B14) -set_property -dict {PACKAGE_PIN T3 } [get_ports pcie_data_rx_n[0]] ; ## MGTXRXN3_112 (JX1.99) (P2.B15) -set_property -dict {PACKAGE_PIN V4 } [get_ports pcie_data_rx_p[1]] ; ## MGTXRXP2_112 (JX1.92) (P2.B19) -set_property -dict {PACKAGE_PIN V3 } [get_ports pcie_data_rx_n[1]] ; ## MGTXRXN2_112 (JX1.94) (P2.B20) -set_property -dict {PACKAGE_PIN Y4 } [get_ports pcie_data_rx_p[2]] ; ## MGTXRXP1_112 (JX1.91) (P2.B23) -set_property -dict {PACKAGE_PIN Y3 } [get_ports pcie_data_rx_n[2]] ; ## MGTXRXN1_112 (JX1.93) (P2.B24) -set_property -dict {PACKAGE_PIN AB4} [get_ports pcie_data_rx_p[3]] ; ## MGTXRXP0_112 (JX1.88) (P2.B27) -set_property -dict {PACKAGE_PIN AB3} [get_ports pcie_data_rx_n[3]] ; ## MGTXRXN0_112 (JX1.90) (P2.B28) -set_property -dict {PACKAGE_PIN R2 } [get_ports pcie_data_tx_p[0]] ; ## MGTXTXP3_112 (JX3.19) (P2.A16) -set_property -dict {PACKAGE_PIN R1 } [get_ports pcie_data_tx_n[0]] ; ## MGTXTXN3_112 (JX3.21) (P2.A17) -set_property -dict {PACKAGE_PIN U2 } [get_ports pcie_data_tx_p[1]] ; ## MGTXTXP2_112 (JX3.14) (P2.A21) -set_property -dict {PACKAGE_PIN U1 } [get_ports pcie_data_tx_n[1]] ; ## MGTXTXN2_112 (JX3.16) (P2.A22) -set_property -dict {PACKAGE_PIN W2 } [get_ports pcie_data_tx_p[2]] ; ## MGTXTXP1_112 (JX3.13) (P2.A25) -set_property -dict {PACKAGE_PIN W1 } [get_ports pcie_data_tx_n[2]] ; ## MGTXTXN1_112 (JX3.15) (P2.A26) -set_property -dict {PACKAGE_PIN AA2} [get_ports pcie_data_tx_p[3]] ; ## MGTXTXP0_112 (JX3.8 ) (P2.A29) -set_property -dict {PACKAGE_PIN AA1} [get_ports pcie_data_tx_n[3]] ; ## MGTXTXN0_112 (JX3.10) (P2.A30) -set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports pcie_rstn] ; ## IO_L19P_T3_13 -set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports pcie_waken] ; ## IO_L20N_T3_13 -set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS33} [get_ports pcie_rstn_good] ; ## IO_L22N_T3_12 - -# Default constraints have LVCMOS25, overwite it - -set_property -dict {IOSTANDARD LVCMOS33} [get_ports iic_scl] ; ## IO_L5P_T0_13 -set_property -dict {IOSTANDARD LVCMOS33} [get_ports iic_sda] ; ## IO_L5N_T0_13 - -set_property PULLUP true [get_ports pcie_rstn] -create_clock -name pcie_ref_clock -period 10 [get_ports pcie_ref_clk_p] - - diff --git a/projects/pzsdr2/ccpci_lvds/system_top.v b/projects/pzsdr2/ccpci_lvds/system_top.v index a8bcc2e3b..aa610357b 100644 --- a/projects/pzsdr2/ccpci_lvds/system_top.v +++ b/projects/pzsdr2/ccpci_lvds/system_top.v @@ -39,176 +39,97 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, - enable, - txnrx, - clk_out, + output enable, + output txnrx, + input clkout_in, - gpio_clksel, - gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status, + inout gpio_clksel, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, - spi_csn, - spi_clk, - spi_mosi, - spi_miso, + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, - pcie_rstn, - pcie_waken, - pcie_ref_clk_p, - pcie_ref_clk_n, - pcie_data_rx_p, - pcie_data_rx_n, - pcie_data_tx_p, - pcie_data_tx_n, + input pcie_rstn, + inout pcie_waken, + input pcie_ref_clk_p, + input pcie_ref_clk_n, + input [ 3:0] pcie_data_rx_p, + input [ 3:0] pcie_data_rx_n, + output [ 3:0] pcie_data_tx_p, + output [ 3:0] pcie_data_tx_n, - pcie_rstn_good); + output pcie_reset_done); - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; + // internal registers - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout iic_scl; - inout iic_sda; - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - - output enable; - output txnrx; - input clk_out; - - inout gpio_clksel; - inout gpio_resetb; - inout gpio_sync; - inout gpio_en_agc; - inout [ 3:0] gpio_ctl; - inout [ 7:0] gpio_status; - - output spi_csn; - output spi_clk; - output spi_mosi; - input spi_miso; - - input pcie_rstn; - inout pcie_waken; - input pcie_ref_clk_p; - input pcie_ref_clk_n; - input [ 3:0] pcie_data_rx_p; - input [ 3:0] pcie_data_rx_n; - output [ 3:0] pcie_data_tx_p; - output [ 3:0] pcie_data_tx_n; - - output pcie_rstn_good; + reg pcie_reset_done_int = 1'b0; // internal signals - reg [3:0] pcie_rstn_cnt0 = 'h00; - reg [3:0] pcie_rstn_cnt1 = 'h00; - reg pcie_rstn_good = 1'b0; - wire pcie_ref_clk; + wire pcie_clk; + wire pcie_rst; wire [63:0] gpio_i; wire [63:0] gpio_o; wire [63:0] gpio_t; - wire [63:0] gpio_ps_i; - // assignments assign pcie_waken = 1'bz; - assign gpio_ps_i[0] = pcie_rstn_good; - assign gpio_ps_i[63:1] = 'h00; + assign pcie_reset_done = pcie_reset_done_int; // PCIe reset monitor - always @(posedge pcie_ref_clk) begin - // If we see a stable low level followed by a stable high level we assume we - // got a good PCIe reset - if (pcie_rstn_cnt0 != 'hf) begin - if (pcie_rstn == 1'b0) begin - pcie_rstn_cnt0 <= pcie_rstn_cnt0 + 1'b1; - end else begin - pcie_rstn_cnt0 <= 'h00; - end - end else if (pcie_rstn_cnt1 != 'hf) begin - if (pcie_rstn == 1'b1) begin - pcie_rstn_cnt1 <= pcie_rstn_cnt1 + 1'b1; - end else begin - pcie_rstn_cnt1 <= 'h00; - end + always @(posedge pcie_clk or posedge pcie_rst) begin + if (pcie_rst == 1'b1) begin + pcie_reset_done_int <= 1'b0; end else begin - pcie_rstn_good <= 1'b1; + pcie_reset_done_int <= 1'b1; end end @@ -255,18 +176,33 @@ module system_top ( .fixed_io_ps_clk (fixed_io_ps_clk), .fixed_io_ps_porb (fixed_io_ps_porb), .fixed_io_ps_srstb (fixed_io_ps_srstb), - .gpio_i (gpio_ps_i), + .gpio_i ({63'd0, pcie_reset_done_int}), .gpio_o (), .gpio_t (), .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .otg_vbusoc (1'b0), + .pcie_clk (pcie_clk), .pcie_data_rxn (pcie_data_rx_n), .pcie_data_rxp (pcie_data_rx_p), .pcie_data_txn (pcie_data_tx_n), .pcie_data_txp (pcie_data_tx_p), .pcie_ref_clk (pcie_ref_clk), + .pcie_rst (pcie_rst), .pcie_rstn (pcie_rstn), + .pl_gpio0_i (gpio_i[31:0]), + .pl_gpio0_o (gpio_o[31:0]), + .pl_gpio0_t (gpio_t[31:0]), + .pl_gpio1_i (gpio_i[63:32]), + .pl_gpio1_o (gpio_o[63:32]), + .pl_gpio1_t (gpio_t[63:32]), + .pl_spi_clk_i (spi_clk), + .pl_spi_clk_o (spi_clk), + .pl_spi_csn_i (spi_csn), + .pl_spi_csn_o (spi_csn), + .pl_spi_sdi_i (spi_miso), + .pl_spi_sdo_i (spi_mosi), + .pl_spi_sdo_o (spi_mosi), .ps_intr_00 (1'b0), .ps_intr_01 (1'b0), .ps_intr_02 (1'b0), @@ -315,20 +251,7 @@ module system_top ( .tx_frame_out_p (tx_frame_out_p), .txnrx (txnrx), .up_enable (gpio_o[47]), - .up_txnrx (gpio_o[48]), - .pl_spi_clk_o(spi_clk), - .pl_spi_clk_i(spi_clk), - .pl_spi_sdo_o(spi_mosi), - .pl_spi_sdo_i(spi_mosi), - .pl_spi_sdi_i(spi_miso), - .pl_spi_csn_o(spi_csn), - .pl_spi_csn_i(spi_csn), - .pl_gpio0_o(gpio_o[31:0]), - .pl_gpio0_t(gpio_t[31:0]), - .pl_gpio0_i(gpio_i[31:0]), - .pl_gpio1_o(gpio_o[63:32]), - .pl_gpio1_t(gpio_t[63:32]), - .pl_gpio1_i(gpio_i[63:32])); + .up_txnrx (gpio_o[48])); endmodule diff --git a/projects/pzsdr2/common/ccpci_bd.tcl b/projects/pzsdr2/common/ccpci_bd.tcl index c0157b824..d42c21121 100644 --- a/projects/pzsdr2/common/ccpci_bd.tcl +++ b/projects/pzsdr2/common/ccpci_bd.tcl @@ -67,6 +67,7 @@ set_property -dict [list CONFIG.PCIEBAR2AXIBAR_0 {0x40000000}] $axi_pcie_x4 set_property -dict [list CONFIG.AXIBAR2PCIEBAR_0 {0x00000000}] $axi_pcie_x4 set axi_pcie_x4_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_pcie_x4_rstgen] +set_property -dict [list CONFIG.C_EXT_RST_WIDTH {16}] $axi_pcie_x4_rstgen set axi_pcie_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_pcie_intc] set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_pcie_intc @@ -88,6 +89,12 @@ ad_connect axi_pcie_x4/mmcm_lock axi_pcie_x4_rstgen/dcm_locked ad_connect axi_pcie_x4/axi_ctl_aclk_out axi_pcie_x4_rstgen/slowest_sync_clk ad_connect pcie_axi_resetn axi_pcie_x4/axi_aresetn +create_bd_port -dir O pcie_rst +create_bd_port -dir O pcie_clk + +ad_connect axi_pcie_x4_rstgen/bus_struct_reset pcie_rst +ad_connect axi_pcie_x4/axi_ctl_aclk_out pcie_clk + # interrupts ad_connect axi_pcie_intc/irq axi_pcie_x4/INTX_MSI_Request diff --git a/projects/pzsdr2/common/ccpci_constr.xdc b/projects/pzsdr2/common/ccpci_constr.xdc index 759e97b9e..edc2b851a 100644 --- a/projects/pzsdr2/common/ccpci_constr.xdc +++ b/projects/pzsdr2/common/ccpci_constr.xdc @@ -21,9 +21,9 @@ set_property -dict {PACKAGE_PIN W2 } [get_ports pcie_data_tx_p[2]] set_property -dict {PACKAGE_PIN W1 } [get_ports pcie_data_tx_n[2]] ; ## U1,W1,MGTXTX1_112_JX3_N,JX3,15,MGTXTX1_112_JX3_N,P2,A26 set_property -dict {PACKAGE_PIN AA2} [get_ports pcie_data_tx_p[3]] ; ## U1,AA2,MGTXTX0_112_JX3_P,JX3,8,MGTXTX0_112_JX3_P,P2,A29 set_property -dict {PACKAGE_PIN AA1} [get_ports pcie_data_tx_n[3]] ; ## U1,AA1,MGTXTX0_112_JX3_N,JX3,10,MGTXTX0_112_JX3_N,P2,A30 -set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS18} [get_ports pcie_rstn] ; ## U1,W20,IO_L19_13_JX2_P,JX2,61,PCIE_PRSNT,P2,A11 -set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS18} [get_ports pcie_waken] ; ## U1,AB20,IO_L20_13_JX2_N,JX2,64,PCIE_WAKEB,P2,B11 -set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS18} [get_ports pcie_rstn_good] ; ## IO_L22N_T3_12, NOT-CONNECTED ???? +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports pcie_rstn] ; ## U1,W20,IO_L19_13_JX2_P,JX2,61,PCIE_PRSNT,P2,A11 +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS25} [get_ports pcie_waken] ; ## U1,AB20,IO_L20_13_JX2_N,JX2,64,PCIE_WAKEB,P2,B11 +set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS25} [get_ports pcie_reset_done] ; ## IO_L22N_T3_12, NOT-CONNECTED ???? set_property PULLUP true [get_ports pcie_rstn] create_clock -name pcie_ref_clock -period 10 [get_ports pcie_ref_clk_p]