From 4e30a5b0bfea44f1264f0906eeadb307859cb18c Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 23 Jun 2015 14:28:02 +0300 Subject: [PATCH] axi_ad9250: Updated altera core to work with axi4lite interface --- library/axi_ad9250/axi_ad9250.v | 8 +- library/axi_ad9250/axi_ad9250_alt.v | 212 --------------------------- library/axi_ad9250/axi_ad9250_hw.tcl | 30 +--- 3 files changed, 9 insertions(+), 241 deletions(-) delete mode 100644 library/axi_ad9250/axi_ad9250_alt.v diff --git a/library/axi_ad9250/axi_ad9250.v b/library/axi_ad9250/axi_ad9250.v index e50856d2b..ef6477685 100644 --- a/library/axi_ad9250/axi_ad9250.v +++ b/library/axi_ad9250/axi_ad9250.v @@ -65,6 +65,7 @@ module axi_ad9250 ( s_axi_aresetn, s_axi_awvalid, s_axi_awaddr, + s_axi_awprot, s_axi_awready, s_axi_wvalid, s_axi_wdata, @@ -75,10 +76,11 @@ module axi_ad9250 ( s_axi_bready, s_axi_arvalid, s_axi_araddr, + s_axi_arprot, s_axi_arready, s_axi_rvalid, - s_axi_rresp, s_axi_rdata, + s_axi_rresp, s_axi_rready); parameter PCORE_ID = 0; @@ -109,6 +111,7 @@ module axi_ad9250 ( input s_axi_aresetn; input s_axi_awvalid; input [31:0] s_axi_awaddr; + input [ 2:0] s_axi_awprot; output s_axi_awready; input s_axi_wvalid; input [31:0] s_axi_wdata; @@ -119,10 +122,11 @@ module axi_ad9250 ( input s_axi_bready; input s_axi_arvalid; input [31:0] s_axi_araddr; + input [ 2:0] s_axi_arprot; output s_axi_arready; output s_axi_rvalid; - output [ 1:0] s_axi_rresp; output [31:0] s_axi_rdata; + output [ 1:0] s_axi_rresp; input s_axi_rready; // internal registers diff --git a/library/axi_ad9250/axi_ad9250_alt.v b/library/axi_ad9250/axi_ad9250_alt.v deleted file mode 100644 index d24f361d8..000000000 --- a/library/axi_ad9250/axi_ad9250_alt.v +++ /dev/null @@ -1,212 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module axi_ad9250_alt ( - - // jesd interface - // rx_clk is (line-rate/40) - - rx_clk, - rx_data, - - // dma interface - - adc_clk, - adc_valid_a, - adc_enable_a, - adc_data_a, - adc_valid_b, - adc_enable_b, - adc_data_b, - adc_dovf, - adc_dunf, - - // axi interface - - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awid, - s_axi_awlen, - s_axi_awsize, - s_axi_awburst, - s_axi_awlock, - s_axi_awcache, - s_axi_awprot, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wlast, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bid, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arid, - s_axi_arlen, - s_axi_arsize, - s_axi_arburst, - s_axi_arlock, - s_axi_arcache, - s_axi_arprot, - s_axi_arready, - s_axi_rvalid, - s_axi_rresp, - s_axi_rdata, - s_axi_rid, - s_axi_rlast, - s_axi_rready); - - parameter PCORE_ID = 0; - parameter PCORE_AXI_ID_WIDTH = 3; - parameter PCORE_DEVICE_TYPE = 0; - - // jesd interface - // rx_clk is (line-rate/40) - - input rx_clk; - input [63:0] rx_data; - - // dma interface - - output adc_clk; - output adc_valid_a; - output adc_enable_a; - output [31:0] adc_data_a; - output adc_valid_b; - output adc_enable_b; - output [31:0] adc_data_b; - input adc_dovf; - input adc_dunf; - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [13:0] s_axi_awaddr; - input [(PCORE_AXI_ID_WIDTH-1):0] s_axi_awid; - input [ 7:0] s_axi_awlen; - input [ 2:0] s_axi_awsize; - input [ 1:0] s_axi_awburst; - input [ 0:0] s_axi_awlock; - input [ 3:0] s_axi_awcache; - input [ 2:0] s_axi_awprot; - output s_axi_awready; - input s_axi_wvalid; - input [31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - input s_axi_wlast; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_bid; - input s_axi_bready; - input s_axi_arvalid; - input [13:0] s_axi_araddr; - input [(PCORE_AXI_ID_WIDTH-1):0] s_axi_arid; - input [ 7:0] s_axi_arlen; - input [ 2:0] s_axi_arsize; - input [ 1:0] s_axi_arburst; - input [ 0:0] s_axi_arlock; - input [ 3:0] s_axi_arcache; - input [ 2:0] s_axi_arprot; - output s_axi_arready; - output s_axi_rvalid; - output [ 1:0] s_axi_rresp; - output [31:0] s_axi_rdata; - output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_rid; - output s_axi_rlast; - input s_axi_rready; - - // defaults - - assign s_axi_bid = s_axi_awid; - assign s_axi_rid = s_axi_arid; - assign s_axi_rlast = 1'd0; - - // ad9250 lite version - - axi_ad9250 #( - .PCORE_ID (PCORE_ID), - .PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE), - .PCORE_IODELAY_GROUP ("adc_if_delay_group")) - i_ad9250 ( - .rx_clk (rx_clk), - .rx_data (rx_data), - .adc_clk (adc_clk), - .adc_valid_a (adc_valid_a), - .adc_enable_a (adc_enable_a), - .adc_data_a (adc_data_a), - .adc_valid_b (adc_valid_b), - .adc_enable_b (adc_enable_b), - .adc_data_b (adc_data_b), - .adc_dovf (adc_dovf), - .adc_dunf (adc_dunf), - .s_axi_aclk (s_axi_aclk), - .s_axi_aresetn (s_axi_aresetn), - .s_axi_awvalid (s_axi_awvalid), - .s_axi_awaddr ({18'd0, s_axi_awaddr}), - .s_axi_awready (s_axi_awready), - .s_axi_wvalid (s_axi_wvalid), - .s_axi_wdata (s_axi_wdata), - .s_axi_wstrb (s_axi_wstrb), - .s_axi_wready (s_axi_wready), - .s_axi_bvalid (s_axi_bvalid), - .s_axi_bresp (s_axi_bresp), - .s_axi_bready (s_axi_bready), - .s_axi_arvalid (s_axi_arvalid), - .s_axi_araddr ({18'd0, s_axi_araddr}), - .s_axi_arready (s_axi_arready), - .s_axi_rvalid (s_axi_rvalid), - .s_axi_rresp (s_axi_rresp), - .s_axi_rdata (s_axi_rdata), - .s_axi_rready (s_axi_rready)); - -endmodule - -// *************************************************************************** -// *************************************************************************** - diff --git a/library/axi_ad9250/axi_ad9250_hw.tcl b/library/axi_ad9250/axi_ad9250_hw.tcl index 62e950133..73cda9a5e 100755 --- a/library/axi_ad9250/axi_ad9250_hw.tcl +++ b/library/axi_ad9250/axi_ad9250_hw.tcl @@ -11,7 +11,7 @@ set_module_property DISPLAY_NAME axi_ad9250 # files add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" -set_fileset_property quartus_synth TOP_LEVEL axi_ad9250_alt +set_fileset_property quartus_synth TOP_LEVEL axi_ad9250 add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v @@ -25,8 +25,7 @@ add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up add_fileset_file axi_ad9250_pnmon.v VERILOG PATH axi_ad9250_pnmon.v add_fileset_file axi_ad9250_if.v VERILOG PATH axi_ad9250_if.v add_fileset_file axi_ad9250_channel.v VERILOG PATH axi_ad9250_channel.v -add_fileset_file axi_ad9250.v VERILOG PATH axi_ad9250.v -add_fileset_file axi_ad9250_alt.v VERILOG PATH axi_ad9250_alt.v TOP_LEVEL_FILE +add_fileset_file axi_ad9250.v VERILOG PATH axi_ad9250.v TOP_LEVEL_FILE # parameters @@ -44,13 +43,6 @@ set_parameter_property PCORE_DEVICE_TYPE TYPE INTEGER set_parameter_property PCORE_DEVICE_TYPE UNITS None set_parameter_property PCORE_DEVICE_TYPE HDL_PARAMETER true -add_parameter PCORE_AXI_ID_WIDTH INTEGER 0 -set_parameter_property PCORE_AXI_ID_WIDTH DEFAULT_VALUE 3 -set_parameter_property PCORE_AXI_ID_WIDTH DISPLAY_NAME PCORE_AXI_ID_WIDTH -set_parameter_property PCORE_AXI_ID_WIDTH TYPE INTEGER -set_parameter_property PCORE_AXI_ID_WIDTH UNITS None -set_parameter_property PCORE_AXI_ID_WIDTH HDL_PARAMETER true - # axi4 slave add_interface s_axi_clock clock end @@ -60,7 +52,7 @@ add_interface s_axi_reset reset end set_interface_property s_axi_reset associatedClock s_axi_clock add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1 -add_interface s_axi axi4 end +add_interface s_axi axi4lite end set_interface_property s_axi associatedClock s_axi_clock set_interface_property s_axi associatedReset s_axi_reset add_interface_port s_axi s_axi_awvalid awvalid Input 1 @@ -80,24 +72,8 @@ add_interface_port s_axi s_axi_rvalid rvalid Output 1 add_interface_port s_axi s_axi_rresp rresp Output 2 add_interface_port s_axi s_axi_rdata rdata Output 32 add_interface_port s_axi s_axi_rready rready Input 1 -add_interface_port s_axi s_axi_awid awid Input PCORE_AXI_ID_WIDTH -add_interface_port s_axi s_axi_awlen awlen Input 8 -add_interface_port s_axi s_axi_awsize awsize Input 3 -add_interface_port s_axi s_axi_awburst awburst Input 2 -add_interface_port s_axi s_axi_awlock awlock Input 1 -add_interface_port s_axi s_axi_awcache awcache Input 4 add_interface_port s_axi s_axi_awprot awprot Input 3 -add_interface_port s_axi s_axi_wlast wlast Input 1 -add_interface_port s_axi s_axi_bid bid Output PCORE_AXI_ID_WIDTH -add_interface_port s_axi s_axi_arid arid Input PCORE_AXI_ID_WIDTH -add_interface_port s_axi s_axi_arlen arlen Input 8 -add_interface_port s_axi s_axi_arsize arsize Input 3 -add_interface_port s_axi s_axi_arburst arburst Input 2 -add_interface_port s_axi s_axi_arlock arlock Input 1 -add_interface_port s_axi s_axi_arcache arcache Input 4 add_interface_port s_axi s_axi_arprot arprot Input 3 -add_interface_port s_axi s_axi_rid rid Output PCORE_AXI_ID_WIDTH -add_interface_port s_axi s_axi_rlast rlast Output 1 # transceiver interface