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jesd204: Add soft logic PCS 

Add soft logic PCS that performs 8b10b encoding for TX and character
pattern alignment and 8b10b decoding for RX.

The modules are intended to be used in combination with a transceiver that
does not have these features implemented in hard logic PCS.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-07-30 21:09:28 +02:00
parent 2d896c0729
commit 4df841addc
15 changed files with 1920 additions and 0 deletions
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library/jesd204/jesd204_soft_pcs_rx/8b10b_decoder.v Normal file
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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact jesd204-licensing@analog.com for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
module jesd204_8b10b_decoder (
input in_disparity,
input [9:0] in_char,
output [7:0] out_char,
output out_charisk,
output out_notintable,
output reg out_disperr,
output reg out_disparity
);
/*
* Only supports the subset of 8b10b that is used by JESD204.
* If non-supported control characters are supplied the output is undefined.
*/
reg [4:0] data5b;
reg notintable5b;
reg [1:0] disparity5b;
reg ignore5b;
reg [2:0] data3b;
reg notintable3b;
reg [1:0] disparity3b;
reg ignore3b;
reg [1:0] total_disparity;
reg notintable_disparity;
// Only detect K28.X
wire charisk = in_char[5:0] == 6'b000011 || in_char[5:0] == 6'b111100;
always @(*) begin
notintable5b <= 1'b0;
disparity5b <= 2'b00;
ignore5b <= 1'b0;
case (in_char[5:0])
6'b000011: begin
data5b <= 5'd28;
disparity5b <= 2'b11;
end
6'b111100: begin
data5b <= 5'd28;
disparity5b <= 2'b01;
end
6'b000110: begin
data5b <= 5'd00;
disparity5b <= 2'b11;
end
6'b111001: begin
data5b <= 5'd00;
disparity5b <= 2'b01;
end
6'b010001: begin
data5b <= 5'd01;
disparity5b <= 2'b11;
end
6'b101110: begin
data5b <= 5'd01;
disparity5b <= 2'b01;
end
6'b010010: begin
data5b <= 5'd02;
disparity5b <= 2'b11;
end
6'b101101: begin
data5b <= 5'd02;
disparity5b <= 2'b01;
end
6'b100011: begin
data5b <= 5'd03;
end
6'b010100: begin
data5b <= 5'd04;
disparity5b <= 2'b11;
end
6'b101011: begin
data5b <= 5'd04;
disparity5b <= 2'b01;
end
6'b100101: begin
data5b <= 5'd05;
end
6'b100110: begin
data5b <= 5'd06;
end
6'b000111: begin
data5b <= 5'd7;
disparity5b <= 2'b11;
ignore5b <= 1'b1;
end
6'b111000: begin
data5b <= 5'd7;
disparity5b <= 2'b01;
ignore5b <= 1'b1;
end
6'b011000: begin
data5b <= 5'd8;
disparity5b <= 2'b11;
end
6'b100111: begin
data5b <= 5'd8;
disparity5b <= 2'b01;
end
6'b101001: begin
data5b <= 5'd9;
end
6'b101010: begin
data5b <= 5'd10;
end
6'b001011: begin
data5b <= 5'd11;
end
6'b101100: begin
data5b <= 5'd12;
end
6'b001101: begin
data5b <= 5'd13;
end
6'b001110: begin
data5b <= 5'd14;
end
6'b000101: begin
data5b <= 5'd15;
disparity5b <= 2'b11;
end
6'b111010: begin
data5b <= 5'd15;
disparity5b <= 2'b01;
end
6'b001001: begin
data5b <= 5'd16;
disparity5b <= 2'b11;
end
6'b110110: begin
data5b <= 5'd16;
disparity5b <= 2'b01;
end
6'b110001: begin
data5b <= 5'd17;
end
6'b110010: begin
data5b <= 5'd18;
end
6'b010011: begin
data5b <= 5'd19;
end
6'b110100: begin
data5b <= 5'd20;
end
6'b010101: begin
data5b <= 5'd21;
end
6'b010110: begin
data5b <= 5'd22;
end
6'b101000: begin
data5b <= 5'd23;
disparity5b <= 2'b11;
end
6'b010111: begin
data5b <= 5'd23;
disparity5b <= 2'b01;
end
6'b001100: begin
data5b <= 5'd24;
disparity5b <= 2'b11;
end
6'b110011: begin
data5b <= 5'd24;
disparity5b <= 2'b01;
end
6'b011001: begin
data5b <= 5'd25;
end
6'b011010: begin
data5b <= 5'd26;
end
6'b100100: begin
data5b <= 5'd27;
disparity5b <= 2'b11;
end
6'b011011: begin
data5b <= 5'd27;
disparity5b <= 2'b01;
end
6'b011100: begin
data5b <= 5'd28;
end
6'b100010: begin
data5b <= 5'd29;
disparity5b <= 2'b11;
end
6'b011101: begin
data5b <= 5'd29;
disparity5b <= 2'b01;
end
6'b100001: begin
data5b <= 5'd30;
disparity5b <= 2'b11;
end
6'b011110: begin
data5b <= 5'd30;
disparity5b <= 2'b01;
end
6'b001010: begin
data5b <= 5'd31;
disparity5b <= 2'b11;
end
6'b110101: begin
data5b <= 5'd31;
disparity5b <= 2'b01;
end
default: begin
data5b <= 5'd00;
notintable5b <= 1'b1;
end
endcase
end
always @(*) begin
ignore3b <= 1'b0;
case (in_char[9:6])
4'b0010: begin
disparity3b <= 2'b11;
end
4'b1101: begin
disparity3b <= 2'b01;
end
4'b1100: begin
disparity3b <= 2'b11;
ignore3b <= 1'b1;
end
4'b0011: begin
disparity3b <= 2'b01;
ignore3b <= 1'b1;
end
4'b0100: begin
disparity3b <= 2'b11;
end
4'b1011: begin
disparity3b <= 2'b01;
end
4'b1000: begin
disparity3b <= 2'b11;
end
4'b0111: begin
disparity3b <= 2'b01;
end
4'b0001: begin
disparity3b <= 2'b11;
end
4'b1110: begin
disparity3b <= 2'b01;
end
default: begin
disparity3b <= 2'b00;
end
endcase
end
always @(*) begin
notintable3b <= 1'b0;
if (charisk == 1'b1) begin
case (in_char[9:6] ^ {4{in_char[5]}})
4'b1101: begin
data3b <= 3'd0;
end
4'b0011: begin
data3b <= 3'd3;
end
4'b1011: begin
data3b <= 3'd4;
end
4'b1010: begin
data3b <= 3'd5;
end
4'b1110: begin
data3b <= 3'd7;
end
default: begin
data3b <= 3'd0;
notintable3b <= 1'b1;
end
endcase
end else begin
case (in_char[9:6])
4'b0010: begin
data3b <= 3'd0;
end
4'b1101: begin
data3b <= 3'd0;
end
4'b1001: begin
data3b <= 3'd1;
end
4'b1010: begin
data3b <= 3'd2;
end
4'b1100: begin
data3b <= 3'd3;
end
4'b0011: begin
data3b <= 3'd3;
end
4'b0100: begin
data3b <= 3'd4;
end
4'b1011: begin
data3b <= 3'd4;
end
4'b0101: begin
data3b <= 3'd5;
end
4'b0110: begin
data3b <= 3'd6;
end
4'b1000: begin
data3b <= 3'd7;
notintable3b <= in_char[5:4] == 2'b00;
end
4'b0111: begin
data3b <= 3'd7;
notintable3b <= in_char[5:4] == 2'b11;
end
4'b0001: begin
data3b <= 3'd7;
notintable3b <= in_char[5:4] != 2'b00;
end
4'b1110: begin
data3b <= 3'd7;
notintable3b <= in_char[5:4] != 2'b11;
end
default: begin
data3b <= 3'd0;
notintable3b <= 1'b1;
end
endcase
end
end
always @(*) begin
if (disparity3b == disparity5b && disparity3b != 2'b00) begin
notintable_disparity <= 1'b1;
end else begin
notintable_disparity <= 1'b0;
end
end
always @(*) begin
total_disparity <= (ignore3b ? 2'b00 : disparity3b) ^ (ignore5b ? 2'b00 : disparity5b);
if (total_disparity[0] == 1'b0 || out_notintable == 1'b1) begin
out_disparity <= in_disparity;
out_disperr <= 1'b0;
end else if (total_disparity[1] == 1'b1) begin
out_disparity <= 1'b0;
out_disperr <= ~in_disparity;
end else begin
out_disparity <= 1'b1;
out_disperr <= in_disparity;
end
end
assign out_char = {data3b,data5b};
assign out_charisk = charisk;
assign out_notintable = notintable5b | notintable3b | notintable_disparity;
endmodule

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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact jesd204-licensing@analog.com for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
module jesd204_soft_pcs_rx #(
parameter NUM_LANES = 1,
parameter DATA_PATH_WIDTH = 4
) (
input clk,
input reset,
input patternalign_en,
input [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data,
output reg [NUM_LANES*DATA_PATH_WIDTH*8-1:0] char,
output reg [NUM_LANES*DATA_PATH_WIDTH-1:0] charisk,
output reg [NUM_LANES*DATA_PATH_WIDTH-1:0] notintable,
output reg [NUM_LANES*DATA_PATH_WIDTH-1:0] disperr
);
localparam LANE_DATA_WIDTH = DATA_PATH_WIDTH * 10;
wire [NUM_LANES*LANE_DATA_WIDTH-1:0] data_aligned;
wire [NUM_LANES*DATA_PATH_WIDTH*8-1:0] char_s;
wire [NUM_LANES*DATA_PATH_WIDTH-1:0] charisk_s;
wire [NUM_LANES*DATA_PATH_WIDTH-1:0] notintable_s;
wire [NUM_LANES*DATA_PATH_WIDTH-1:0] disperr_s;
reg [NUM_LANES-1:0] disparity = {NUM_LANES{1'b0}};
wire [DATA_PATH_WIDTH:0] disparity_chain[0:NUM_LANES-1];
always @(posedge clk) begin
char <= char_s;
charisk <= charisk_s;
notintable <= notintable_s;
disperr <= disperr_s;
end
generate
genvar lane;
genvar i;
for (lane = 0; lane < NUM_LANES; lane = lane + 1) begin: gen_lane
jesd204_pattern_align #(
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
) i_pattern_align (
.clk(clk),
.reset(reset),
.patternalign_en(patternalign_en),
.in_data(data[LANE_DATA_WIDTH*lane+:LANE_DATA_WIDTH]),
.out_data(data_aligned[LANE_DATA_WIDTH*lane+:LANE_DATA_WIDTH])
);
assign disparity_chain[lane][0] = disparity[lane];
always @(posedge clk) begin
if (reset == 1'b1) begin
disparity[lane] <= 1'b0;
end else begin
disparity[lane] <= disparity_chain[lane][DATA_PATH_WIDTH];
end
end
for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_dpw
localparam j = DATA_PATH_WIDTH * lane + i;
jesd204_8b10b_decoder i_dec (
.in_char(data_aligned[j*10+:10]),
.out_char(char_s[j*8+:8]),
.out_charisk(charisk_s[j]),
.out_notintable(notintable_s[j]),
.out_disperr(disperr_s[j]),
.in_disparity(disparity_chain[lane][i]),
.out_disparity(disparity_chain[lane][i+1])
);
end
end
endgenerate
endmodule

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library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl Normal file
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#
# The ADI JESD204 Core is released under the following license, which is
# different than all other HDL cores in this repository.
#
# Please read this, and understand the freedoms and responsibilities you have
# by using this source code/core.
#
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
#
# This core is free software, you can use run, copy, study, change, ask
# questions about and improve this core. Distribution of source, or resulting
# binaries (including those inside an FPGA or ASIC) require you to release the
# source of the entire project (excluding the system libraries provide by the
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License version 2
# along with this source code, and binary. If not, see
# <http://www.gnu.org/licenses/>.
#
# Commercial licenses (with commercial support) of this JESD204 core are also
# available under terms different than the General Public License. (e.g. they
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
# core with any corresponding source code.) For these alternate terms you must
# purchase a license from Analog Devices Technology Licensing Office. Users
# interested in such a license should contact jesd204-licensing@analog.com for
# more information. This commercial license is sub-licensable (if you purchase
# chips from Analog Devices, incorporate them into your PCB level product, and
# purchase a JESD204 license, end users of your product will also have a
# license to use this core in a commercial setting without releasing their
# source code).
#
# In addition, we kindly ask you to acknowledge ADI in any program, application
# or publication in which you use this JESD204 HDL core. (You are not required
# to do so; it is up to your common sense to decide whether you want to comply
# with this request or not.) For general publications, we suggest referencing :
# “The design and implementation of the JESD204 HDL Core used in this project
# is copyright © 2016-2017, Analog Devices, Inc.”
#
package require qsys
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
ad_ip_create jesd204_soft_pcs_rx "ADI JESD204 Transmit Soft PCS"
set_module_property INTERNAL true
# files
ad_ip_files jesd204_soft_pcs_rx [list \
jesd204_soft_pcs_rx.v \
pattern_align.v \
8b10b_decoder.v \
]
# clock
add_interface clock clock end
add_interface_port clock clk clk Input 1
# reset
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
add_interface_port reset reset reset Input 1
# interfaces
add_interface rx_phy conduit start
#set_interface_property rx_phy associatedClock clock
#set_interface_property rx_phy associatedReset reset
add_interface_port rx_phy char char Output 32
add_interface_port rx_phy charisk charisk Output 4
add_interface_port rx_phy disperr disperr Output 4
add_interface_port rx_phy notintable notintable Output 4
add_interface_port rx_phy patternalign_en patternalign_en Input 1
add_interface rx_raw_data conduit end
#set_interface_property rx_raw_data associatedClock clock
#set_interface_property rx_raw_data associatedReset reset
add_interface_port rx_raw_data data raw_data Input 40

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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact jesd204-licensing@analog.com for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
module jesd204_pattern_align #(
parameter DATA_PATH_WIDTH = 4
) (
input clk,
input reset,
input patternalign_en,
input [DATA_PATH_WIDTH*10-1:0] in_data,
output [DATA_PATH_WIDTH*10-1:0] out_data
);
localparam [9:0] PATTERN_P = 10'b1010000011;
localparam [9:0] PATTERN_N = 10'b0101111100;
reg [1:0] match_counter = 2'h0;
reg pattern_sync = 1'b0;
reg pattern_match = 1'b0;
reg [3:0] align = 4'h0;
reg [1:0] cooldown = 2'h3;
reg [8:0] data_d1 = 9'h00;
reg [DATA_PATH_WIDTH*10+2:0] aligned_data_stage1;
reg [DATA_PATH_WIDTH*10-1:0] aligned_data_stage2;
wire [(DATA_PATH_WIDTH+1)*10-2:0] full_data;
assign full_data = {in_data,data_d1};
assign out_data = aligned_data_stage2;
/* 2-stage cascade of 3:1 and 4:1 muxes */
integer i;
always @(*) begin
for (i = 0; i < DATA_PATH_WIDTH*10+3; i = i + 1) begin
if (i < DATA_PATH_WIDTH*10+1) begin
case (align[3:2])
2'b00: aligned_data_stage1[i] <= full_data[i];
2'b01: aligned_data_stage1[i] <= full_data[i+4];
2'b10: aligned_data_stage1[i] <= full_data[i+8];
default: aligned_data_stage1[i] <= 1'b0;
endcase
end else begin
case (align[2])
1'b0: aligned_data_stage1[i] <= full_data[i];
default: aligned_data_stage1[i] <= full_data[i+4];
endcase
end
end
aligned_data_stage2 <= aligned_data_stage1[align[1:0]+:DATA_PATH_WIDTH*10];
end
always @(posedge clk) begin
data_d1 <= in_data[DATA_PATH_WIDTH*10-9+:9];
end
always @(posedge clk) begin
if (out_data[9:0] == PATTERN_P || out_data[9:0] == PATTERN_N) begin
pattern_match <= 1'b1;
end else begin
pattern_match <= 1'b0;
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
cooldown <= 2'h3;
align <= 4'h0;
end else begin
if (cooldown != 2'h0) begin
cooldown <= cooldown - 1'b1;
end else if (patternalign_en == 1'b1 && pattern_sync == 1'b0 &&
pattern_match == 1'b0) begin
cooldown <= 2'h3;
if (align == 'h9) begin
align <= 4'h0;
end else begin
align <= align + 1'b1;
end
end
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
pattern_sync <= 1'b0;
match_counter <= 2'h0;
end else begin
if (match_counter == 2'h0) begin
pattern_sync <= 1'b0;
end else if (match_counter == 2'h3) begin
pattern_sync <= 1'b1;
end
if (pattern_match == 1'b1) begin
if (match_counter != 2'h3) begin
match_counter <= match_counter + 1'b1;
end
end else begin
if (match_counter != 2'h0) begin
match_counter <= match_counter - 1'b1;
end
end
end
end
endmodule

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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact jesd204-licensing@analog.com for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
module jesd204_8b10b_encoder (
input in_disparity,
input [7:0] in_char,
input in_charisk,
output [9:0] out_char,
output out_disparity
);
/*
* Only supports the subset of 8b10b that is used by JESD204.
* If non-supported control characters are supplied the output is undefined.
*/
reg [5:0] data6b;
reg [5:0] out6b;
reg may_invert6b;
reg disparity6b;
reg [3:0] data4b;
reg [3:0] out4b;
reg may_invert4b;
reg disparity4b;
wire disparity4b_in;
reg alt7;
always @(*) begin
if (in_charisk == 1'b1) begin
// Assume K28.x
data6b <= 6'b000011;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
end else begin
case (in_char[4:0])
5'd00: begin
data6b <= 6'b000110;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
end
5'd01: begin
data6b <= 6'b010001;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
end
5'd02: begin
data6b <= 6'b010010;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
end
5'd03: begin
data6b <= 6'b100011;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
end
5'd04: begin
data6b <= 6'b010100;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
end
5'd05: begin
data6b <= 6'b100101;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
end
5'd06: begin
data6b <= 6'b100110;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
end
5'd07: begin
data6b <= 6'b111000;
may_invert6b <= 1'b1;
disparity6b <= 1'b0;
end
5'd08: begin
data6b <= 6'b011000;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
end
5'd09: begin
data6b <= 6'b101001;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
end
5'd10: begin
data6b <= 6'b101010;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
end
5'd11: begin
data6b <= 6'b001011;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
end
5'd12: begin
data6b <= 6'b101100;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
end
5'd13: begin
data6b <= 6'b001101;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
end
5'd14: begin
data6b <= 6'b001110;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
end
5'd15: begin
data6b <= 6'b000101;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
end
5'd16: begin
data6b <= 6'b001001;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
end
5'd17: begin
data6b <= 6'b110001;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
end
5'd18: begin
data6b <= 6'b110010;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
end
5'd19: begin
data6b <= 6'b010011;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
end
5'd20: begin
data6b <= 6'b110100;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
end
5'd21: begin
data6b <= 6'b010101;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
end
5'd22: begin
data6b <= 6'b010110;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
end
5'd23: begin
data6b <= 6'b101000;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
end
5'd24: begin
data6b <= 6'b001100;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
end
5'd25: begin
data6b <= 6'b011001;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
end
5'd26: begin
data6b <= 6'b011010;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
end
5'd27: begin
data6b <= 6'b100100;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
end
5'd28: begin
data6b <= 6'b011100;
may_invert6b <= 1'b0;
disparity6b <= 1'b0;
end
5'd29: begin
data6b <= 6'b100010;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
end
5'd30: begin
data6b <= 6'b100001;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
end
default: begin
data6b <= 6'b001010;
may_invert6b <= 1'b1;
disparity6b <= 1'b1;
end
endcase
end
end
always @(*) begin
if (in_charisk == 1'b1) begin
alt7 <= 1'b1;
end else begin
// case (in_char[4:0])
// 5'd11, 5'd13, 5'd14: alt7 <= in_disparity;
// 5'd17, 5'd18, 5'd20: alt7 <= ~in_disparity;
// default: alt7 <= 1'b0;
// endcase
// Slightly better packing
case ({may_invert6b,data6b[5:4]})
3'b000: alt7 <= in_disparity;
3'b011: alt7 <= ~in_disparity;
default: alt7 <= 1'b0;
endcase
end
end
always @(*) begin
case (in_char[7:5])
3'd0: begin
data4b <= 4'b0010;
may_invert4b <= 1'b1;
disparity4b <= 1'b1;
end
3'd1: begin
data4b <= 4'b1001;
may_invert4b <= in_charisk;
disparity4b <= 1'b0;
end
3'd2: begin
data4b <= 4'b1010;
may_invert4b <= in_charisk;
disparity4b <= 1'b0;
end
3'd3: begin
data4b <= 4'b1100;
may_invert4b <= 1'b1;
disparity4b <= 1'b0;
end
3'd4: begin
data4b <= 4'b0100;
may_invert4b <= 1'b1;
disparity4b <= 1'b1;
end
3'd5: begin
data4b <= 4'b0101;
may_invert4b <= in_charisk;
disparity4b <= 1'b0;
end
3'd6: begin
data4b <= 4'b0110;
may_invert4b <= in_charisk;
disparity4b <= 1'b0;
end
default: begin
if (alt7 == 1'b1) begin
data4b <= 4'b0001;
end else begin
data4b <= 4'b1000;
end
may_invert4b <= 1'b1;
disparity4b <= 1'b1;
end
endcase
end
assign disparity4b_in = in_disparity ^ disparity6b;
assign out_disparity = disparity4b_in ^ disparity4b;
always @(*) begin
if (in_disparity == 1'b0 && may_invert6b == 1'b1) begin
out6b <= ~data6b;
end else begin
out6b <= data6b;
end
if (disparity4b_in == 1'b0 && may_invert4b == 1'b1) begin
out4b <= ~data4b;
end else begin
out4b <= data4b;
end
end
assign out_char = {out4b,out6b};
endmodule

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library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v Normal file
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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact jesd204-licensing@analog.com for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
module jesd204_soft_pcs_tx #(
parameter NUM_LANES = 1,
parameter DATA_PATH_WIDTH = 4
) (
input clk,
input reset,
input [NUM_LANES*DATA_PATH_WIDTH*8-1:0] char,
input [NUM_LANES*DATA_PATH_WIDTH-1:0] charisk,
output reg [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data
);
reg [NUM_LANES-1:0] disparity = 'h00;
wire [DATA_PATH_WIDTH:0] disparity_chain[0:NUM_LANES-1];
wire [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data_s;
always @(posedge clk) begin
data <= data_s;
end
generate
genvar lane;
genvar i;
for (lane = 0; lane < NUM_LANES; lane = lane + 1) begin: gen_lane
assign disparity_chain[lane][0] = disparity[lane];
always @(posedge clk) begin
if (reset == 1'b1) begin
disparity[lane] <= 1'b0;
end else begin
disparity[lane] <= disparity_chain[lane][DATA_PATH_WIDTH];
end
end
for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_dpw
localparam j = DATA_PATH_WIDTH * lane + i;
jesd204_8b10b_encoder i_enc (
.in_char(char[j*8+:8]),
.in_charisk(charisk[j]),
.out_char(data_s[j*10+:10]),
.in_disparity(disparity_chain[lane][i]),
.out_disparity(disparity_chain[lane][i+1])
);
end
end
endgenerate
endmodule

85
library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl Normal file
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#
# The ADI JESD204 Core is released under the following license, which is
# different than all other HDL cores in this repository.
#
# Please read this, and understand the freedoms and responsibilities you have
# by using this source code/core.
#
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
#
# This core is free software, you can use run, copy, study, change, ask
# questions about and improve this core. Distribution of source, or resulting
# binaries (including those inside an FPGA or ASIC) require you to release the
# source of the entire project (excluding the system libraries provide by the
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License version 2
# along with this source code, and binary. If not, see
# <http://www.gnu.org/licenses/>.
#
# Commercial licenses (with commercial support) of this JESD204 core are also
# available under terms different than the General Public License. (e.g. they
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
# core with any corresponding source code.) For these alternate terms you must
# purchase a license from Analog Devices Technology Licensing Office. Users
# interested in such a license should contact jesd204-licensing@analog.com for
# more information. This commercial license is sub-licensable (if you purchase
# chips from Analog Devices, incorporate them into your PCB level product, and
# purchase a JESD204 license, end users of your product will also have a
# license to use this core in a commercial setting without releasing their
# source code).
#
# In addition, we kindly ask you to acknowledge ADI in any program, application
# or publication in which you use this JESD204 HDL core. (You are not required
# to do so; it is up to your common sense to decide whether you want to comply
# with this request or not.) For general publications, we suggest referencing :
# “The design and implementation of the JESD204 HDL Core used in this project
# is copyright © 2016-2017, Analog Devices, Inc.”
#
package require qsys
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
ad_ip_create jesd204_soft_pcs_tx "ADI JESD204 Transmit Soft PCS"
set_module_property INTERNAL true
# files
ad_ip_files jesd204_soft_pcs_tx [list \
jesd204_soft_pcs_tx.v \
8b10b_encoder.v \
]
# clock
add_interface clock clock end
add_interface_port clock clk clk Input 1
# reset
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
add_interface_port reset reset reset Input 1
# interfaces
add_interface tx_phy conduit start
#set_interface_property tx_phy associatedClock clock
#set_interface_property tx_phy associatedReset reset
add_interface_port tx_phy char char Input 32
add_interface_port tx_phy charisk charisk Input 4
add_interface tx_raw_data conduit end
#set_interface_property data associatedClock clock
#set_interface_property data associatedReset reset
add_interface_port tx_raw_data data raw_data Output 40

8
library/jesd204/tb/soft_pcs_8b10b_sequence_tb Executable file
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#!/bin/bash
SOURCE="soft_pcs_8b10b_sequence_tb.v"
SOURCE+=" ../jesd204_soft_pcs_tx/8b10b_encoder.v"
SOURCE+=" ../jesd204_soft_pcs_rx/8b10b_decoder.v"
cd `dirname $0`
source run_tb.sh

132
library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v Normal file
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@ -0,0 +1,132 @@
//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact jesd204-licensing@analog.com for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
module soft_pcs_8b10b_sequence_tb;
parameter VCD_FILE = "soft_pcs_8b10b_sequence_tb.vcd";
`include "tb_base.v"
// Send a random sequence of characters to the decoder and make sure the
// decoder produces the same character sequence and no disparity or
// not-in-table errors
wire [9:0] raw_data;
reg [7:0] encoder_char = 'h00;
reg encoder_charisk = 1'b0;
wire [7:0] decoder_char;
wire decoder_charisk;
wire decoder_notintable;
wire decoder_disperr;
reg encoder_disparity = 1'b0;
wire encoder_disparity_s;
reg decoder_disparity = 1'b0;
wire decoder_disparity_s;
integer x;
reg inject_enc_disparity_error = 1'b0;
/*
always @(posedge clk) begin
if ({$random} % 256 == 0) begin
inject_enc_disparity_error <= 1'b1;
end else begin
inject_enc_disparity_error <= 1'b0;
end
end
*/
always @(posedge clk) begin
x = {$random} % (256 + 5);
if (x < 256) begin
encoder_char <= x & 8'hff;
encoder_charisk <= 1'b0;
end else begin
case (x - 256)
0: encoder_char <= {3'd0,5'd28};
1: encoder_char <= {3'd3,5'd28};
2: encoder_char <= {3'd4,5'd28};
3: encoder_char <= {3'd5,5'd28};
4: encoder_char <= {3'd7,5'd28};
endcase
encoder_charisk <= 1'b1;
end
encoder_disparity <= encoder_disparity_s ^ inject_enc_disparity_error;
decoder_disparity <= decoder_disparity_s;
end
jesd204_8b10b_encoder i_enc (
.in_char(encoder_char),
.in_charisk(encoder_charisk),
.out_char(raw_data),
.in_disparity(encoder_disparity),
.out_disparity(encoder_disparity_s)
);
jesd204_8b10b_decoder i_dec (
.in_char(raw_data),
.out_char(decoder_char),
.out_notintable(decoder_notintable),
.out_disperr(decoder_disperr),
.out_charisk(decoder_charisk),
.in_disparity(decoder_disparity),
.out_disparity(decoder_disparity_s)
);
wire char_mismatch = encoder_char != decoder_char;
wire charisk_mismatch = encoder_charisk != decoder_charisk;
always @(posedge clk) begin
if (char_mismatch == 1'b1 || charisk_mismatch == 1'b1 ||
decoder_notintable == 1'b1 || decoder_disperr == 1'b1) begin
failed <= 1'b1;
end
end
endmodule

8
library/jesd204/tb/soft_pcs_8b10b_table_tb Executable file
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@ -0,0 +1,8 @@
#!/bin/bash
SOURCE="soft_pcs_8b10b_table_tb.v"
SOURCE+=" ../jesd204_soft_pcs_tx/8b10b_encoder.v"
SOURCE+=" ../jesd204_soft_pcs_rx/8b10b_decoder.v"
cd `dirname $0`
source run_tb.sh

148
library/jesd204/tb/soft_pcs_8b10b_table_tb.v Normal file
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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact jesd204-licensing@analog.com for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
module soft_pcs_8b10b_table_tb;
parameter VCD_FILE = "soft_pcs_8b10b_table_tb.vcd";
`include "tb_base.v"
// Build a table of all valid 8b10b words using the encoder and then check
// for every possible 10-bit value that the decoder correctly reports the
// not-in-table flag
reg [1023:0] valid_table = 'h00;
reg [8:0] counter = 10'h00;
reg [7:0] encoder_char = 8'h00;
reg encoder_charisk = 1'b0;
reg encoder_disparity = 1'b0;
wire [9:0] encoder_raw;
wire [7:0] decoder_char;
wire decoder_notintable;
wire decoder_charisk;
reg [9:0] decoder_raw = 10'h00;
reg build_k28 = 1'b0;
reg build_table = 1'b1;
always @(posedge clk) begin
counter <= counter + 1'b1;
if (counter == 'h1ff) begin
build_k28 <= 1'b1;
end else if (counter == 'h9 && build_k28 == 1'b1) begin
build_table <= 1'b0;
end
end
always @(*) begin
encoder_disparity <= counter[0];
if (build_k28 == 1'b0) begin
encoder_char <= counter[8:1];
encoder_charisk <= 1'b0;
end else begin
case (counter[8:1])
0: encoder_char <= {3'd0,5'd28};
1: encoder_char <= {3'd3,5'd28};
2: encoder_char <= {3'd4,5'd28};
3: encoder_char <= {3'd5,5'd28};
4: encoder_char <= {3'd7,5'd28};
endcase
encoder_charisk <= 1'b1;
end
end
jesd204_8b10b_encoder i_enc (
.in_char(encoder_char),
.in_charisk(encoder_charisk),
.in_disparity(encoder_disparity),
.out_char(encoder_raw)
);
always @(posedge clk) begin
if (build_table == 1'b1) begin
valid_table[encoder_raw] <= 1'b1;
end
end
always @(posedge clk) begin
if (build_table == 1'b0) begin
decoder_disparity <= ~decoder_disparity;
if (decoder_disparity == 1'b1 && decoder_raw != 'h3ff) begin
decoder_raw <= decoder_raw + 1'b1;
end
end
end
reg decoder_disparity = 1'b0;
wire decoder_disparity_s;
always @(posedge clk) begin
end
jesd204_8b10b_decoder i_dec (
.in_char(build_table ? encoder_raw : decoder_raw),
.out_char(decoder_char),
.out_notintable(decoder_notintable),
.out_charisk(decoder_charisk),
.in_disparity(decoder_disparity),
.out_disparity(decoder_disparity_s)
);
wire decoder_should_be_in_table = valid_table[decoder_raw];
always @(posedge clk) begin
if (build_table == 1'b0) begin
if (decoder_notintable == decoder_should_be_in_table) begin
$display("%b.%b, %d", decoder_raw[9:6], decoder_raw[5:0],
decoder_should_be_in_table);
failed <= 1'b1;
end
end
end
endmodule

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#!/bin/bash
SOURCE="soft_pcs_loopback_tb.v"
SOURCE+=" ../jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v ../jesd204_soft_pcs_tx/8b10b_encoder.v"
SOURCE+=" ../jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v ../jesd204_soft_pcs_rx/8b10b_decoder.v"
SOURCE+=" ../jesd204_soft_pcs_rx/pattern_align.v"
cd `dirname $0`
source run_tb.sh

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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A pcsTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact jesd204-licensing@analog.com for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
module soft_pcs_loopback_tb;
parameter VCD_FILE = "soft_pcs_loopback_tb.vcd";
parameter DATA_PATH_WIDTH = 4;
`include "tb_base.v"
reg [7:0] tx_char = {3'd5,5'd28};
reg tx_charisk = 1'b1;
reg [8*DATA_PATH_WIDTH-1:0] tx_char_pcs = 'h00;
reg [DATA_PATH_WIDTH-1:0] tx_charisk_pcs = 'h00;
wire [7:0] rx_char;
wire rx_charisk;
wire rx_notintable;
wire rx_disperr;
wire [8*DATA_PATH_WIDTH-1:0] rx_char_pcs;
wire [DATA_PATH_WIDTH-1:0] rx_charisk_pcs;
wire [DATA_PATH_WIDTH-1:0] rx_notintable_pcs;
wire [DATA_PATH_WIDTH-1:0] rx_disperr_pcs;
reg rx_pattern_align_en = 1'b1;
wire [10*DATA_PATH_WIDTH-1:0] data_aligned;
wire [10*DATA_PATH_WIDTH+9:0] data_aligned_full;
reg [8:0] data_aligned_d1 = 'h00;
reg [10*DATA_PATH_WIDTH-1:0] data_unaligned = 'h00;
reg [3:0] bitshift = 'h00;
integer clk_div = 0;
wire pcs_clk = clk_div < DATA_PATH_WIDTH / 2 ? 1'b1 : 1'b0;
reg pcs_reset = 1'b1;
always @(posedge pcs_clk) begin
pcs_reset <= 1'b0;
end
always @(posedge clk) begin
if (clk_div == DATA_PATH_WIDTH - 1) begin
clk_div <= 0;
end else begin
clk_div <= clk_div + 1;
end
end
always @(posedge pcs_clk) begin
data_aligned_d1 <= data_aligned[DATA_PATH_WIDTH*10-1:DATA_PATH_WIDTH*10-9];
end
assign data_aligned_full = {data_aligned,data_aligned_d1};
always @(*) begin
data_unaligned <= data_aligned_full[bitshift+:DATA_PATH_WIDTH*10];
end
jesd204_soft_pcs_tx #(
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
) i_soft_pcs_tx (
.clk(pcs_clk),
.reset(pcs_reset),
.char(tx_char_pcs),
.charisk(tx_charisk_pcs),
.data(data_aligned)
);
jesd204_soft_pcs_rx #(
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
) i_soft_pcs_rx (
.clk(pcs_clk),
.reset(pcs_reset),
.patternalign_en(rx_pattern_align_en),
.data(data_unaligned),
.char(rx_char_pcs),
.charisk(rx_charisk_pcs),
.notintable(rx_notintable_pcs),
.disperr(rx_disperr_pcs)
);
always @(posedge clk) begin
tx_char_pcs <= {tx_char,tx_char_pcs[DATA_PATH_WIDTH*8-1:8]};
tx_charisk_pcs <= {tx_charisk,tx_charisk_pcs[DATA_PATH_WIDTH-1:1]};
end
integer rx_mux_select = 0;
always @(posedge clk) begin
if (rx_mux_select == DATA_PATH_WIDTH - 1) begin
rx_mux_select <= 0;
end else begin
rx_mux_select <= rx_mux_select + 1;
end
end
assign rx_charisk = rx_charisk_pcs[rx_mux_select];
assign rx_notintable = rx_notintable_pcs[rx_mux_select];
assign rx_disperr = rx_disperr_pcs[rx_mux_select];
generate
genvar i;
for (i = 0; i < 8; i = i + 1) begin
assign rx_char[i] = rx_char_pcs[rx_mux_select*8+i];
end
endgenerate
integer counter = 0;
localparam STATE_SEND_ALIGN = 0;
localparam STATE_SEND_DATA = 1;
reg state = STATE_SEND_ALIGN;
reg [7:0] rx_compare = 'h00;
always @(posedge clk) begin
case(state)
STATE_SEND_ALIGN: begin
tx_char <= {3'd5,5'd28};
tx_charisk <= 1'b1;
// Worst case alignment time is 40 * DATA_PATH_WIDTH
if (counter < DATA_PATH_WIDTH * 60) begin
rx_pattern_align_en <= 1'b1;
end else begin
rx_pattern_align_en <= 1'b0;
end
if (counter == DATA_PATH_WIDTH * 64) begin
state <= STATE_SEND_DATA;
counter <= 0;
rx_compare <= 'h00;
end else begin
counter <= counter + 1'b1;
end
end
STATE_SEND_DATA: begin
if (tx_charisk == 1'b1) begin
tx_char <= 'h00;
end else begin
tx_char <= tx_char + 1'b1;
end
tx_charisk <= 1'b0;
if (rx_charisk == 1'b0) begin
rx_compare <= rx_compare + 1'b1;
if (rx_char != rx_compare || rx_disperr == 1'b1 || rx_notintable == 1'b1) begin
failed <= 1'b1;
end
end else begin
rx_compare <= 'h00;
end
if (rx_char == 'd255) begin
state <= STATE_SEND_ALIGN;
bitshift <= {$random} % 10;
end
end
endcase
end
endmodule

7
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#!/bin/bash
SOURCE="soft_pcs_pattern_align_tb.v"
SOURCE+=" ../jesd204_soft_pcs_rx/pattern_align.v"
cd `dirname $0`
source run_tb.sh

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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact jesd204-licensing@analog.com for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
module soft_pcs_pattern_align_tb;
parameter VCD_FILE = "soft_pcs_pattern_align_tb.vcd";
localparam [9:0] PATTERN_P = 10'b1010000011;
localparam [9:0] PATTERN_N = 10'b0101111100;
`define TIMEOUT 1000000
`include "tb_base.v"
integer counter = 0;
reg [3:0] bitshift = 4'd0;
reg [9:0] comma_unaligned;
reg comma_sync = 1'b0;
wire [9:0] comma_aligned;
reg [9:0] comma = PATTERN_P;
wire comma_match = comma == comma_aligned;
always @(posedge clk) begin
if (counter == 63) begin
if (comma_sync != 1'b1) begin
failed <= 1'b1;
end
comma_sync <= 1'b0;
counter <= 0;
bitshift <= {$random} % 10;
comma <= {$random} % 2 ? PATTERN_P : PATTERN_N;
end else begin
counter <= counter + 1'b1;
// Takes two clock cycles for the new value to propagate
if (counter > 1) begin
// Shouldn't loose sync after it gained it
if (comma_match == 1'b1) begin
comma_sync <= 1'b1;
end else if (comma_sync == 1'b1) begin
failed <= 1'b1;
end
end
end
end
always @(*) begin
case (bitshift)
4'd0: comma_unaligned <= comma[9:0];
4'd1: comma_unaligned <= {comma[0],comma[9:1]};
4'd2: comma_unaligned <= {comma[1:0],comma[9:2]};
4'd3: comma_unaligned <= {comma[2:0],comma[9:3]};
4'd4: comma_unaligned <= {comma[3:0],comma[9:4]};
4'd5: comma_unaligned <= {comma[4:0],comma[9:5]};
4'd6: comma_unaligned <= {comma[5:0],comma[9:6]};
4'd7: comma_unaligned <= {comma[6:0],comma[9:7]};
4'd8: comma_unaligned <= {comma[7:0],comma[9:8]};
default: comma_unaligned <= {comma[8:0],comma[9]};
endcase
end
jesd204_pattern_align #(
.DATA_PATH_WIDTH(1)
) i_pa (
.clk(clk),
.reset(1'b0),
.patternalign_en(1'b1),
.in_data(comma_unaligned),
.out_data(comma_aligned)
);
endmodule