adi_ip_alt.tcl: Add comments to all proc
Istvan Csomortani
István Csomortáni
parent
f2b3b7f493
commit
4d966500a8
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@ -1,7 +1,16 @@
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###################################################################################################
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###################################################################################################
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# keep interface-mess out of the way - keeping it pretty is a waste of time
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## Define an interface for Platform Designer.
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#
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# \param[type] - Type of the interface, valid values are : clock, reset, reset-n,
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# signal, intr
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# \param[name] - The name of the interface
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# \param[dir] - The direction of the interface
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# \param[width] - The width of the interface
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# \param[arg_1] - Optional argument to define the associated clock for a reset
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# interface
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# \param[arg_2] - Optional argument to define the associated reset sink for a
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# reset interface
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#
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proc ad_alt_intf {type name dir width {arg_1 ""} {arg_2 ""}} {
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if {([string equal -nocase ${type} "clock"]) && ([string equal -nocase ${dir} "input"])} {
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@ -65,15 +74,28 @@ proc ad_alt_intf {type name dir width {arg_1 ""} {arg_2 ""}} {
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}
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}
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## Create a point-to-point conduit interface.
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#
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# \param[if_name] - the name of the interface
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# \param[if_port] - the type of signal for this port, which must be unique
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# \param[port] - the name of the port, this name must match the signal name
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# in HDL
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# \param[dir] - the direction of the signal, expected values: input/output/bidir
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# \param[width] - the width of the port, in bits
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#
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proc ad_conduit {if_name if_port port dir width} {
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add_interface $if_name conduit end
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add_interface_port $if_name $port $if_port $dir $width
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}
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###################################################################################################
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###################################################################################################
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## Create an IP.
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#
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# \param[pname] - name of the IP, general equivalent to the top HDL module name
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# \param[pdisplay_name] - displayed name
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# \param[pelabfunction] - name of the elaboration callback function
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# \param[pcomposefunction] - name of the composition callback function
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#
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proc ad_ip_create {pname pdisplay_name {pelabfunction ""} {pcomposefunction ""}} {
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set_module_property NAME $pname
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@ -91,9 +113,15 @@ proc ad_ip_create {pname pdisplay_name {pelabfunction ""} {pcomposefunction ""}}
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}
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}
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###################################################################################################
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###################################################################################################
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## Create an IP parameter.
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#
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# \param[pname] - name of the IP, general equivalent to the top HDL module name
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# \param[ptype] - the data type of the parameter
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# \param[pdefault] - the initial value of the parameter
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# \param[phdl] - define if the parameter is an HDL parameter or not
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# \param[properties] - can define different properties for the parameter, must be
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# a list of {key, value} pairs
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#
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proc ad_ip_parameter {pname ptype pdefault {phdl true} {properties {}}} {
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if {$pname eq "DEVICE_FAMILY"} {
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@ -113,9 +141,10 @@ proc ad_ip_parameter {pname ptype pdefault {phdl true} {properties {}}} {
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}
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}
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###################################################################################################
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###################################################################################################
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## Adds the generic ADI spec parameters to the current IP, with the help of
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# adi_add_device_spec_param. The spec parameter list is auto_gen_param_list,
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# from library/scripts/adi_intel_device_info_enc.tcl.
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#
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proc adi_add_auto_fpga_spec_params {} {
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global ad_hdl_dir
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@ -131,8 +160,22 @@ proc adi_add_auto_fpga_spec_params {} {
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}
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}
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###################################################################################################
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## Generate validation properties for a parameter, using predefined ranges or
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# set of values (the definition of the ranges can be found in
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# library/scripts/adi_intel_device_info_enc.tcl).
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#
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# In Intel callback flow, one cannot directly change a parameter value, the value
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# can only be calculated/deduced from the environment.
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# Adding a second parameter with the same name followed by "_MANUAL", will add
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# in the environment the desired value that is still constrained to a predefined
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# set. Having the second parameter is not enough, to activate the manual
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# overwriting of a parameter one must call the adi_add_indep_spec_params_overwrite
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# process.
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#
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# \param[param] - Name of the HDL parameter. The list of accepted values for
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# the parameter are defined with the same name as the parameter's one(lower case),
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# followed by "_list"
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#
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proc adi_add_device_spec_param {param} {
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global auto_gen_param_list
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@ -178,8 +221,11 @@ proc adi_add_device_spec_param {param} {
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set_parameter_property ${param}_MANUAL ALLOWED_RANGES $ranges
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}
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###################################################################################################
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## Creates a boolean type parameter that allows this user to manually overwrite
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# parameter values.
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#
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# \param[param] - Name of the HDL parameter.
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#
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proc adi_add_indep_spec_params_overwrite {param} {
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add_parameter ${param}_USER_OVERWRITE BOOLEAN 0
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set_parameter_property ${param}_USER_OVERWRITE DISPLAY_NAME "Manually overwrite $param parameter"
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@ -187,8 +233,13 @@ proc adi_add_indep_spec_params_overwrite {param} {
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set_parameter_property ${param}_USER_OVERWRITE GROUP {FPGA info}
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}
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###################################################################################################
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## In this process the IP parameters are compared against predefined parameter lists
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# in library/scripts/adi_intel_device_info_enc.tcl. For the matching parameters,
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# a search is started after a pair *_USER_OVERWRITE(boolean) parameter. If the pair
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# *_USER_OVERWRITE parameter is found, and its value is true, the target parameter
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# will take the value of the *_MANUAL parameter. The GUI parameter is set as
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# writable in the qsys GUI (${parameter_name} is replaced by ${parameter_name}_MANUAL).
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#
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proc info_param_validate {} {
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global ad_hdl_dir
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global fpga_technology
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@ -270,7 +321,7 @@ proc info_param_validate {} {
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}
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}
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# display manual(writable) or auto(non-writable) parametes
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# display manual(writable) or auto(non-writable) parameters
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foreach p $validate_list {
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set_parameter_property ${p}_MANUAL VISIBLE [expr $auto_populate ? false : true]
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set_parameter_property $p VISIBLE $auto_populate
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@ -290,9 +341,11 @@ proc info_param_validate {} {
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}
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}
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###################################################################################################
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###################################################################################################
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## Add source files to an IP, automatically find the file type using its extension.
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#
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# \param[pname] - name of the IP, general equivalent to the top HDL module name
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# \param[pfile] - name of the file
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#
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proc ad_ip_addfile {pname pfile} {
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set pmodule [file tail $pfile]
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@ -322,6 +375,11 @@ proc ad_ip_addfile {pname pfile} {
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}
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}
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## Add source files to an IP, automatically find the file type using its extension.
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#
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# \param[pname] - name of the IP, general equivalent to the top HDL module name
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# \param[pfile] - name of the file
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#
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proc ad_ip_files {pname pfiles {pfunction ""}} {
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add_fileset quartus_synth QUARTUS_SYNTH $pfunction ""
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@ -337,9 +395,12 @@ proc ad_ip_files {pname pfiles {pfunction ""}} {
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}
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}
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###################################################################################################
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###################################################################################################
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## Infer an AXI4 Lite memory mapped interface.
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#
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# \param[aclk] - name of the interface clock
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# \param[arstn] - name fo the interface reset
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# \param[addr_width] - address width of the read and write channels
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#
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proc ad_ip_intf_s_axi {aclk arstn {addr_width 16}} {
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add_interface s_axi_clock clock end
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@ -373,6 +434,3 @@ proc ad_ip_intf_s_axi {aclk arstn {addr_width 16}} {
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add_interface_port s_axi s_axi_rready rready Input 1
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}
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###################################################################################################
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###################################################################################################
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