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ad9361/all/system_constr.xdc: remove manual clock definition 

Having a clock assigned manually to the clk output pin of the axi_ad9361
let the Vivado timing engine to not ignore the clock insertion delay when
analyzing paths between clk_0 and the manually created clock that has
the same source (clk_0), resulting in timing failure.
main
Laszlo Nagy 2019-02-27 16:51:43 +00:00 committed by AndreiGrozav
parent bd79a0040e
commit 4b13274c55
7 changed files with 0 additions and 7 deletions
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1
projects/adrv9361z7035/common/adrv9361z7035_constr_cmos.xdc
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@ -38,5 +38,4 @@ set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18} [get_ports tx_gnd[1]
# clocks # clocks
create_clock -name rx_clk -period 8 [get_ports rx_clk_in] create_clock -name rx_clk -period 8 [get_ports rx_clk_in]
create_clock -name ad9361_clk -period 8 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]

1
projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc
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@ -38,5 +38,4 @@ set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS} [get_ports tx_data_o
# clocks # clocks
create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p] create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p]
create_clock -name ad9361_clk -period 4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]

1
projects/adrv9364z7020/common/adrv9364z7020_constr_cmos.xdc
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@ -38,5 +38,4 @@ set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS25} [get_ports tx_gnd[1]
# clocks # clocks
create_clock -name rx_clk -period 8 [get_ports rx_clk_in] create_clock -name rx_clk -period 8 [get_ports rx_clk_in]
create_clock -name ad9361_clk -period 8 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]

1
projects/adrv9364z7020/common/adrv9364z7020_constr_lvds.xdc
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@ -38,5 +38,4 @@ set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVDS_25} [get_ports tx_data_o
# clocks # clocks
create_clock -name rx_clk -period 8 [get_ports rx_clk_in_p] create_clock -name rx_clk -period 8 [get_ports rx_clk_in_p]
create_clock -name ad9361_clk -period 8 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]

1
projects/fmcomms5/zc702/system_constr.xdc
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@ -132,7 +132,6 @@ set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS25} [get_ports gpio_ca
create_clock -name rx_0_clk -period 5.00 [get_ports rx_clk_in_0_p] create_clock -name rx_0_clk -period 5.00 [get_ports rx_clk_in_0_p]
create_clock -name rx_1_clk -period 5.00 [get_ports rx_clk_in_1_p] create_clock -name rx_1_clk -period 5.00 [get_ports rx_clk_in_1_p]
create_clock -name ad9361_clk -period 5.00 [get_pins i_system_wrapper/system_i/axi_ad9361_0/clk]
# gpio (pmods) # gpio (pmods)

1
projects/fmcomms5/zc706/system_constr.xdc
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@ -132,4 +132,3 @@ set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports gpio_ca
create_clock -name rx_0_clk -period 4.00 [get_ports rx_clk_in_0_p] create_clock -name rx_0_clk -period 4.00 [get_ports rx_clk_in_0_p]
create_clock -name rx_1_clk -period 4.00 [get_ports rx_clk_in_1_p] create_clock -name rx_1_clk -period 4.00 [get_ports rx_clk_in_1_p]
create_clock -name ad9361_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9361_0/clk]

1
projects/fmcomms5/zcu102/system_constr.xdc
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@ -132,4 +132,3 @@ set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS18} [get_ports gpio_ca
create_clock -name rx_0_clk -period 4.00 [get_ports rx_clk_in_0_p] create_clock -name rx_0_clk -period 4.00 [get_ports rx_clk_in_0_p]
create_clock -name rx_1_clk -period 4.00 [get_ports rx_clk_in_1_p] create_clock -name rx_1_clk -period 4.00 [get_ports rx_clk_in_1_p]
create_clock -name ad9361_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9361_0/clk]