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library/IPs: Auto-generate bd.tcl Update 

Remove all bd.tcl and respecting the previous commit, update *_ip.tcl to
auto-generate bd.tcl for:

  - axi_ad5766/axi_ad5766_ip.tcl
  - axi_ad6676/axi_ad6676_ip.tcl
  - axi_ad9122/axi_ad9122_ip.tcl
  - axi_ad9144/axi_ad9144_ip.tcl
  - axi_ad9152/axi_ad9152_ip.tcl
  - axi_ad9162/axi_ad9162_ip.tcl
  - axi_ad9250/axi_ad9250_ip.tcl
  - axi_ad9265/axi_ad9265_ip.tcl
  - axi_ad9361/axi_ad9361_ip.tcl
  - axi_ad9371/axi_ad9371_ip.tcl
  - axi_ad9434/axi_ad9434_ip.tcl
  - axi_ad9467/axi_ad9467_ip.tcl
  - axi_ad9625/axi_ad9625_ip.tcl
  - axi_ad9671/axi_ad9671_ip.tcl
  - axi_ad9680/axi_ad9680_ip.tcl
  - axi_ad9684/axi_ad9684_ip.tcl
  - axi_ad9739a/axi_ad9739a_ip.tcl
  - axi_ad9963/axi_ad9963_ip.tcl
  - axi_adrv9009/axi_adrv9009_ip.tcl
  - axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl
  - axi_hdmi_tx/axi_hdmi_tx_ip.tcl
  - xilinx/axi_adxcvr/Makefile
  - xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
  - xilinx/util_adxcvr/Makefile
  - xilinx/util_adxcvr/util_adxcvr_ip.tcl
main
AndreiGrozav 2019-03-14 17:25:36 +02:00 committed by AndreiGrozav
parent 99412a503e
commit 4ae5a6d3d8
48 changed files with 92 additions and 1106 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
library/axi_ad5766/axi_ad5766_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_ad5766
adi_ip_files axi_ad5766 [list \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
@ -18,7 +20,8 @@ adi_ip_files axi_ad5766 [list \
adi_ip_properties axi_ad5766
adi_ip_bd axi_ad5766 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_ad5766 "bd/bd.tcl"
adi_ip_add_core_dependencies { \
analog.com:user:util_cdc:1.0 \

50
library/axi_ad5766/bd/bd.tcl
View File

@ -1,50 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/axi_ad6676/axi_ad6676_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_ad6676
adi_ip_files axi_ad6676 [list \
"axi_ad6676.v" \
@ -10,7 +12,8 @@ adi_ip_files axi_ad6676 [list \
adi_ip_properties axi_ad6676
adi_ip_bd axi_ad6676 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_ad6676 "bd/bd.tcl"
adi_ip_add_core_dependencies { \
analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \

49
library/axi_ad6676/bd/bd.tcl
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@ -1,49 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/axi_ad9122/axi_ad9122_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_ad9122
adi_ip_files axi_ad9122 [list \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
@ -35,7 +37,8 @@ adi_ip_files axi_ad9122 [list \
adi_ip_properties axi_ad9122
adi_ip_bd axi_ad9122 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_ad9122 "bd/bd.tcl"
set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]

50
library/axi_ad9122/bd/bd.tcl
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@ -1,50 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/axi_ad9144/axi_ad9144_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_ad9144
adi_ip_files axi_ad9144 [list \
"axi_ad9144.v" \
@ -10,7 +12,8 @@ adi_ip_files axi_ad9144 [list \
adi_ip_properties axi_ad9144
adi_ip_bd axi_ad9144 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_ad9144 "bd/bd.tcl"
adi_ip_add_core_dependencies { \
analog.com:user:ad_ip_jesd204_tpl_dac:1.0 \

50
library/axi_ad9144/bd/bd.tcl
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@ -1,50 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/axi_ad9152/axi_ad9152_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_ad9152
adi_ip_files axi_ad9152 [list \
"axi_ad9152.v" \
@ -10,7 +12,8 @@ adi_ip_files axi_ad9152 [list \
adi_ip_properties axi_ad9152
adi_ip_bd axi_ad9152 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_ad9152 "bd/bd.tcl"
adi_ip_add_core_dependencies { \
analog.com:user:ad_ip_jesd204_tpl_dac:1.0 \

50
library/axi_ad9152/bd/bd.tcl
View File

@ -1,50 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/axi_ad9162/axi_ad9162_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_ad9162
adi_ip_files axi_ad9162 [list \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
@ -30,7 +32,8 @@ adi_ip_files axi_ad9162 [list \
adi_ip_properties axi_ad9162
adi_ip_bd axi_ad9122 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_ad9122 "bd/bd.tcl"
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]

50
library/axi_ad9162/bd/bd.tcl
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@ -1,50 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/axi_ad9250/axi_ad9250_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_ad9250
adi_ip_files axi_ad9250 [list \
"axi_ad9250.v" \
@ -10,7 +12,8 @@ adi_ip_files axi_ad9250 [list \
adi_ip_properties axi_ad9250
adi_ip_bd axi_ad9250 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_ad9250 "bd/bd.tcl"
adi_ip_add_core_dependencies { \
analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \

50
library/axi_ad9250/bd/bd.tcl
View File

@ -1,50 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/axi_ad9265/axi_ad9265_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_ad9265
adi_ip_files axi_ad9265 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
@ -30,7 +32,8 @@ adi_ip_files axi_ad9265 [list \
adi_ip_properties axi_ad9265
adi_ip_bd axi_ad9265 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_ad9265 "bd/bd.tcl"
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]

50
library/axi_ad9265/bd/bd.tcl
View File

@ -1,50 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/axi_ad9361/axi_ad9361_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_ad9361
adi_ip_files axi_ad9361 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
@ -54,7 +56,8 @@ adi_ip_files axi_ad9361 [list \
adi_ip_properties axi_ad9361
adi_ip_ttcl axi_ad9361 "$ad_hdl_dir/library/common/ad_pps_receiver_constr.ttcl"
adi_ip_bd axi_ad9361 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_ad9361 "bd/bd.tcl"
set_property driver_value 0 [ipx::get_ports *rx_clk_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *rx_frame_in* -of_objects [ipx::current_core]]

50
library/axi_ad9361/bd/bd.tcl
View File

@ -1,50 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/axi_ad9371/axi_ad9371_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_ad9371
adi_ip_files axi_ad9371 [list \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
@ -40,7 +42,8 @@ adi_ip_files axi_ad9371 [list \
adi_ip_properties axi_ad9371
adi_ip_bd axi_ad9371 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_ad9371 "bd/bd.tcl"
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]

50
library/axi_ad9371/bd/bd.tcl
View File

@ -1,50 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/axi_ad9434/axi_ad9434_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_ad9434
adi_ip_files axi_ad9434 [list \
"$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \
@ -31,7 +33,8 @@ adi_ip_files axi_ad9434 [list \
adi_ip_properties axi_ad9434
adi_ip_bd axi_ad9122 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_ad9122 "bd/bd.tcl"
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]

50
library/axi_ad9434/bd/bd.tcl
View File

@ -1,50 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/axi_ad9467/axi_ad9467_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_ad9467
adi_ip_files axi_ad9467 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
@ -29,7 +31,8 @@ adi_ip_files axi_ad9467 [list \
adi_ip_properties axi_ad9467
adi_ip_bd axi_ad9467 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_ad9467 "bd/bd.tcl"
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]

50
library/axi_ad9467/bd/bd.tcl
View File

@ -1,50 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/axi_ad9625/axi_ad9625_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_ad9625
adi_ip_files axi_ad9625 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
@ -28,7 +30,8 @@ adi_ip_files axi_ad9625 [list \
adi_ip_properties axi_ad9625
adi_ip_bd axi_ad9122 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_ad9122 "bd/bd.tcl"
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]]

50
library/axi_ad9625/bd/bd.tcl
View File

@ -1,50 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/axi_ad9671/axi_ad9671_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_ad9671
adi_ip_files axi_ad9671 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
@ -28,7 +30,8 @@ adi_ip_files axi_ad9671 [list \
adi_ip_properties axi_ad9671
adi_ip_bd axi_ad9371 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_ad9371 "bd/bd.tcl"
set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]

50
library/axi_ad9671/bd/bd.tcl
View File

@ -1,50 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/axi_ad9680/axi_ad9680_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_ad9680
adi_ip_files axi_ad9680 [list \
"axi_ad9680.v" \
@ -10,7 +12,8 @@ adi_ip_files axi_ad9680 [list \
adi_ip_properties axi_ad9680
adi_ip_bd axi_ad9680 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_ad9680 "bd/bd.tcl"
adi_ip_add_core_dependencies { \
analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \

50
library/axi_ad9680/bd/bd.tcl
View File

@ -1,50 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/axi_ad9684/axi_ad9684_ip.tcl
View File

@ -4,6 +4,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_ad9684
adi_ip_files axi_ad9684 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
@ -32,7 +34,8 @@ adi_ip_files axi_ad9684 [list \
adi_ip_properties axi_ad9684
adi_ip_bd axi_ad9684 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_ad9684 "bd/bd.tcl"
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]

50
library/axi_ad9684/bd/bd.tcl
View File

@ -1,50 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/axi_ad9739a/axi_ad9739a_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_ad9739a
adi_ip_files axi_ad9739a [list \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
@ -32,7 +34,8 @@ adi_ip_files axi_ad9739a [list \
adi_ip_properties axi_ad9739a
adi_ip_bd axi_ad9739a "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_ad9739a "bd/bd.tcl"
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]

50
library/axi_ad9739a/bd/bd.tcl
View File

@ -1,50 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/axi_ad9963/axi_ad9963_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_ad9963
adi_ip_files axi_ad9963 [list \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
@ -43,7 +45,8 @@ adi_ip_files axi_ad9963 [list \
adi_ip_properties axi_ad9963
adi_ip_bd axi_ad9963 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_ad9963 "bd/bd.tcl"
set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]

50
library/axi_ad9963/bd/bd.tcl
View File

@ -1,50 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/axi_adrv9009/axi_adrv9009_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_adrv9009
adi_ip_files axi_adrv9009 [list \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
@ -40,7 +42,8 @@ adi_ip_files axi_adrv9009 [list \
adi_ip_properties axi_adrv9009
adi_ip_bd axi_adrv9009 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_adrv9009 "bd/bd.tcl"
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]

50
library/axi_adrv9009/bd/bd.tcl
View File

@ -1,50 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_fmcadc5_sync
adi_ip_files axi_fmcadc5_sync [list \
"$ad_hdl_dir/library/xilinx/common/ad_data_out.v" \
@ -15,7 +17,8 @@ adi_ip_files axi_fmcadc5_sync [list \
adi_ip_properties axi_fmcadc5_sync
adi_ip_bd axi_fmcadc5_sync "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_fmcadc5_sync "bd/bd.tcl"
ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

50
library/axi_fmcadc5_sync/bd/bd.tcl
View File

@ -1,50 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_hdmi_tx
adi_ip_files axi_hdmi_tx [list \
"$ad_hdl_dir/library/common/ad_mem.v" \
@ -29,7 +31,8 @@ adi_ip_files axi_hdmi_tx [list \
adi_ip_properties axi_hdmi_tx
adi_ip_bd axi_ad9122 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_ad9122 "bd/bd.tcl"
set_property driver_value 0 [ipx::get_ports *hsync* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *vsync* -of_objects [ipx::current_core]]

50
library/axi_hdmi_tx/bd/bd.tcl
View File

@ -1,50 +0,0 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

1
library/xilinx/axi_adxcvr/Makefile
View File

@ -12,7 +12,6 @@ XILINX_DEPS += axi_adxcvr_ip.tcl
XILINX_DEPS += axi_adxcvr_mdrp.v
XILINX_DEPS += axi_adxcvr_mstatus.v
XILINX_DEPS += axi_adxcvr_up.v
XILINX_DEPS += bd/bd.tcl
XILINX_DEPS += ../../interfaces/if_xcvr_ch.xml
XILINX_DEPS += ../../interfaces/if_xcvr_ch_rtl.xml

5
library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
View File

@ -3,6 +3,8 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create axi_adxcvr
adi_ip_files axi_adxcvr [list \
"$ad_hdl_dir/library/common/up_axi.v" \
@ -18,7 +20,8 @@ adi_ip_files axi_adxcvr [list \
adi_ip_properties axi_adxcvr
adi_ip_infer_mm_interfaces axi_adxcvr
adi_ip_bd axi_adxcvr "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd axi_adxcvr "bd/bd.tcl"
set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]

20
library/xilinx/axi_adxcvr/bd/bd.tcl
View File

@ -1,20 +0,0 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_override $ip " \
XCVR_TYPE \
FPGA_VOLTAGE"
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

1
library/xilinx/util_adxcvr/Makefile
View File

@ -5,7 +5,6 @@
LIBRARY_NAME := util_adxcvr
XILINX_DEPS += bd/bd.tcl
XILINX_DEPS += util_adxcvr.v
XILINX_DEPS += util_adxcvr_constr.xdc
XILINX_DEPS += util_adxcvr_ip.tcl

12
library/xilinx/util_adxcvr/bd/bd.tcl
View File

@ -1,12 +0,0 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_override $ip "XCVR_TYPE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

5
library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
View File

@ -3,6 +3,8 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_init_bd_tcl
adi_ip_create util_adxcvr
adi_ip_files util_adxcvr [list \
"$ad_hdl_dir/library/scripts/common_bd.tcl" \
@ -15,7 +17,8 @@ adi_ip_files util_adxcvr [list \
adi_ip_properties_lite util_adxcvr
adi_ip_bd util_adxcvr "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_auto_fill_bd_tcl
adi_ip_bd util_adxcvr "bd/bd.tcl"
ipx::remove_all_bus_interface [ipx::current_core]