cn0506_mii: Add support on a10soc
AndreiGrozav
AndreiGrozav
parent
fbb3a154ff
commit
4941d89fff
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := cn0506_a10soc
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M_DEPS += ../common/cn0506_qsys.tcl
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M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl
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M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
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include ../../scripts/project-intel.mk
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@ -0,0 +1,3 @@
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- Connect on FMC A HPC(V57.1)
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- VADJ = 1.8V
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- MII mode. Connected to HPS (EMAC1-PHY0 and EMAC2-PHY1).
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@ -0,0 +1,6 @@
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create_clock -period "40.000 ns" -name mii_rx_clk_a [get_ports {mii_rx_clk_a}]
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create_clock -period "40.000 ns" -name mii_rx_clk_b [get_ports {mii_rx_clk_b}]
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create_clock -period "40.000 ns" -name mii_tx_clk_a [get_ports {mii_tx_clk_a}]
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create_clock -period "40.000 ns" -name mii_tx_clk_b [get_ports {mii_tx_clk_b}]
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source ../../scripts/adi_env.tcl
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source ../../scripts/adi_project_intel.tcl
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adi_project cn0506_a10soc
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source $ad_hdl_dir/projects/common/a10soc/a10soc_system_assign.tcl
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# Note: This projects requires a hardware rework to function correctly.
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# The rework connects FMC header pins directly to the FPGA so that they can be
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# accessed by the fabric.
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#
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# Changes required (D08-FMC):
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#
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# R610: DNI -> R0
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# R611: DNI -> R0
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# R612: R0 -> DNI
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# R613: R0 -> DNI
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# R620: DNI -> R0
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# R632: DNI -> R0
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# R621: R0 -> DNI
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# R633: R0 -> DNI
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set_location_assignment PIN_G14 -to mii_rx_clk_a ; ## G06 FMCA_HPC_LA00_CC_P
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set_location_assignment PIN_E12 -to mii_rx_er_a ; ## D08 FMCA_HPC_LA01_CC_P
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set_location_assignment PIN_B9 -to mii_rx_dv_a ; ## H14 FMCA_HPC_LA07_N
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set_location_assignment PIN_C13 -to mii_rxd_a[0] ; ## H07 FMCA_HPC_LA02_P
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set_location_assignment PIN_D13 -to mii_rxd_a[1] ; ## H08 FMCA_HPC_LA02_N
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set_location_assignment PIN_C14 -to mii_rxd_a[2] ; ## G09 FMCA_HPC_LA03_P
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set_location_assignment PIN_D14 -to mii_rxd_a[3] ; ## G10 FMCA_HPC_LA03_N
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set_location_assignment PIN_H13 -to mii_tx_clk_a ; ## H11 FMCA_HPC_LA04_N
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set_location_assignment PIN_A9 -to mii_tx_en_a ; ## H13 FMCA_HPC_LA07_P
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set_location_assignment PIN_A12 -to mii_txd_a[0] ; ## D14 FMCA_HPC_LA09_P
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set_location_assignment PIN_A13 -to mii_txd_a[1] ; ## D15 FMCA_HPC_LA09_N
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set_location_assignment PIN_A10 -to mii_txd_a[2] ; ## C10 FMCA_HPC_LA06_P
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set_location_assignment PIN_B10 -to mii_txd_a[3] ; ## C11 FMCA_HPC_LA06_N
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set_instance_assignment -name IO_STANDARD "1.8 V" -to mii_rx_clk_a
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set_instance_assignment -name IO_STANDARD "1.8 V" -to mii_rx_dv_a
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set_instance_assignment -name IO_STANDARD "1.8 V" -to mii_rxd_a
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set_instance_assignment -name IO_STANDARD "1.8 V" -to mii_tx_clk_a
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set_instance_assignment -name IO_STANDARD "1.8 V" -to mii_tx_en_a
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set_instance_assignment -name IO_STANDARD "1.8 V" -to mii_txd_a
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set_location_assignment PIN_C9 -to mdio_fmc_a ; ## H16 FMCA_HPC_LA11_P
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set_location_assignment PIN_D9 -to mdc_fmc_a ; ## H17 FMCA_HPC_LA11_N
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set_instance_assignment -name IO_STANDARD "1.8 V" -to mdio_fmc_a
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to mdio_fmc_a
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set_instance_assignment -name IO_STANDARD "1.8 V" -to mdc_fmc_a
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set_location_assignment PIN_D4 -to reset_a ; ## H19 FMCA_HPC_LA15_P
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set_location_assignment PIN_H12 -to link_st_a ; ## H10 FMCA_HPC_LA04_P
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set_location_assignment PIN_B12 -to mii_crs_a ; ## G13 FMCA_HPC_LA08_N
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set_location_assignment PIN_B11 -to led_0_a ; ## G12 FMCA_HPC_LA08_P
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set_location_assignment PIN_M12 -to led_ar_c_c2m ; ## G15 FMCA_HPC_LA12_P
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set_location_assignment PIN_N13 -to led_ar_a_c2m ; ## G16 FMCA_HPC_LA12_N
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set_location_assignment PIN_J11 -to led_al_c_c2m ; ## D17 FMCA_HPC_LA13_P
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set_location_assignment PIN_K11 -to led_al_a_c2m ; ## D18 FMCA_HPC_LA13_N
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set_instance_assignment -name IO_STANDARD "1.8 V" -to reset_a
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set_instance_assignment -name IO_STANDARD "1.8 V" -to link_st_a
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set_instance_assignment -name IO_STANDARD "1.8 V" -to mii_crs_a
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set_instance_assignment -name IO_STANDARD "1.8 V" -to led_0_a
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set_instance_assignment -name IO_STANDARD "1.8 V" -to led_ar_c_c2m
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set_instance_assignment -name IO_STANDARD "1.8 V" -to led_ar_a_c2m
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set_instance_assignment -name IO_STANDARD "1.8 V" -to led_al_c_c2m
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set_instance_assignment -name IO_STANDARD "1.8 V" -to led_al_a_c2m
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set_location_assignment PIN_G7 -to mii_rx_clk_b ; ## C22 FMCA_HPC_LA18_CC_P
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set_location_assignment PIN_F9 -to mii_rx_er_b ; ## D20 FMCA_HPC_LA17_CC_P
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set_location_assignment PIN_E2 -to mii_rx_dv_b ; ## H29 FMCA_HPC_LA24_N
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set_location_assignment PIN_G5 -to mii_rxd_b[0] ; ## H22 FMCA_HPC_LA19_P
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set_location_assignment PIN_G6 -to mii_rxd_b[1] ; ## H23 FMCA_HPC_LA19_N
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set_location_assignment PIN_C3 -to mii_rxd_b[2] ; ## G21 FMCA_HPC_LA20_P
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set_location_assignment PIN_C4 -to mii_rxd_b[3] ; ## G22 FMCA_HPC_LA20_N
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set_location_assignment PIN_F3 -to mii_tx_clk_b ; ## G28 FMCA_HPC_LA25_N
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set_location_assignment PIN_E1 -to mii_tx_en_b ; ## H28 FMCA_HPC_LA24_P
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set_location_assignment PIN_C2 -to mii_txd_b[0] ; ## H25 FMCA_HPC_LA21_P
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set_location_assignment PIN_D3 -to mii_txd_b[1] ; ## H26 FMCA_HPC_LA21_N
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set_location_assignment PIN_F4 -to mii_txd_b[2] ; ## G24 FMCA_HPC_LA22_P
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set_location_assignment PIN_G4 -to mii_txd_b[3] ; ## G25 FMCA_HPC_LA22_N
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set_instance_assignment -name IO_STANDARD "1.8 V" -to mii_rx_clk_b
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set_instance_assignment -name IO_STANDARD "1.8 V" -to mii_rx_dv_b
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set_instance_assignment -name IO_STANDARD "1.8 V" -to mii_rxd_b
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set_instance_assignment -name IO_STANDARD "1.8 V" -to mii_tx_clk_b
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set_instance_assignment -name IO_STANDARD "1.8 V" -to mii_tx_en_b
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set_instance_assignment -name IO_STANDARD "1.8 V" -to mii_txd_b
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set_location_assignment PIN_L5 -to mdio_fmc_b ; ## H31 FMCA_HPC_LA28_P
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set_location_assignment PIN_M5 -to mdc_fmc_b ; ## H32 FMCA_HPC_LA28_N
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set_instance_assignment -name IO_STANDARD "1.8 V" -to mdio_fmc_b
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to mdio_fmc_b
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set_instance_assignment -name IO_STANDARD "1.8 V" -to mdc_fmc_b
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set_location_assignment PIN_D5 -to reset_b ; ## H20 FMCA_HPC_LA15_N
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set_location_assignment PIN_E3 -to link_st_b ; ## G27 FMCA_HPC_LA25_P
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set_location_assignment PIN_D1 -to mii_crs_b ; ## D24 FMCA_HPC_LA23_N
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set_location_assignment PIN_C1 -to led_0_b ; ## D23 FMCA_HPC_LA23_P
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set_location_assignment PIN_F2 -to led_bl_c_c2m ; ## D26 FMCA_HPC_LA26_P
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set_location_assignment PIN_G2 -to led_bl_a_c2m ; ## D27 FMCA_HPC_LA26_N
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set_location_assignment PIN_D6 -to led_br_c_c2m ; ## G18 FMCA_HPC_LA16_P
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set_location_assignment PIN_E6 -to led_br_a_c2m ; ## G19 FMCA_HPC_LA16_N
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set_instance_assignment -name IO_STANDARD "1.8 V" -to reset_b
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set_instance_assignment -name IO_STANDARD "1.8 V" -to link_st_b
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set_instance_assignment -name IO_STANDARD "1.8 V" -to mii_crs_b
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set_instance_assignment -name IO_STANDARD "1.8 V" -to led_0_b
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set_instance_assignment -name IO_STANDARD "1.8 V" -to led_bl_c_c2m
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set_instance_assignment -name IO_STANDARD "1.8 V" -to led_bl_a_c2m
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set_instance_assignment -name IO_STANDARD "1.8 V" -to led_br_c_c2m
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set_instance_assignment -name IO_STANDARD "1.8 V" -to led_br_a_c2m
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execute_flow -compile
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@ -0,0 +1,5 @@
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source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl
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source ../common/cn0506_qsys.tcl
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2019 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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// clock and resets
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input sys_clk,
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input sys_resetn,
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// hps-ddr4 (32)
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input hps_ddr_ref_clk,
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output [ 0:0] hps_ddr_clk_p,
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output [ 0:0] hps_ddr_clk_n,
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output [ 16:0] hps_ddr_a,
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output [ 1:0] hps_ddr_ba,
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output [ 0:0] hps_ddr_bg,
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output [ 0:0] hps_ddr_cke,
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output [ 0:0] hps_ddr_cs_n,
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output [ 0:0] hps_ddr_odt,
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output [ 0:0] hps_ddr_reset_n,
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output [ 0:0] hps_ddr_act_n,
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output [ 0:0] hps_ddr_par,
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input [ 0:0] hps_ddr_alert_n,
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inout [ 3:0] hps_ddr_dqs_p,
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inout [ 3:0] hps_ddr_dqs_n,
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inout [ 31:0] hps_ddr_dq,
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inout [ 3:0] hps_ddr_dbi_n,
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input hps_ddr_rzq,
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// hps-ethernet
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input [ 0:0] hps_eth_rxclk,
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input [ 0:0] hps_eth_rxctl,
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input [ 3:0] hps_eth_rxd,
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output [ 0:0] hps_eth_txclk,
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output [ 0:0] hps_eth_txctl,
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output [ 3:0] hps_eth_txd,
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output [ 0:0] hps_eth_mdc,
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inout [ 0:0] hps_eth_mdio,
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// hps-sdio
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output [ 0:0] hps_sdio_clk,
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inout [ 0:0] hps_sdio_cmd,
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inout [ 7:0] hps_sdio_d,
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// hps-usb
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input [ 0:0] hps_usb_clk,
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input [ 0:0] hps_usb_dir,
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input [ 0:0] hps_usb_nxt,
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output [ 0:0] hps_usb_stp,
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inout [ 7:0] hps_usb_d,
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// hps-uart
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input [ 0:0] hps_uart_rx,
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output [ 0:0] hps_uart_tx,
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// hps-i2c (shared w fmc-a, fmc-b)
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inout [ 0:0] hps_i2c_sda,
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inout [ 0:0] hps_i2c_scl,
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// hps-gpio (max-v-u16)
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inout [ 3:0] hps_gpio,
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// gpio (max-v-u21)
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input [ 7:0] gpio_bd_i,
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output [ 3:0] gpio_bd_o,
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// mii interfaces
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output reset_a,
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output mdc_fmc_a,
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inout mdio_fmc_a,
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input [3:0] mii_rxd_a,
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input mii_rx_er_a,
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input mii_rx_dv_a,
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input mii_rx_clk_a,
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output [3:0] mii_txd_a,
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output mii_tx_en_a,
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input mii_tx_clk_a,
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input link_st_a,
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input mii_crs_a,
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input led_0_a,
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output reset_b,
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output mdc_fmc_b,
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inout mdio_fmc_b,
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input [3:0] mii_rxd_b,
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input mii_rx_er_b,
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input mii_rx_dv_b,
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input mii_rx_clk_b,
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output [3:0] mii_txd_b,
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output mii_tx_en_b,
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input mii_tx_clk_b,
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input link_st_b,
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input mii_crs_b,
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input led_0_b,
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// LEDs
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output led_ar_c_c2m,
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output led_ar_a_c2m,
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output led_al_c_c2m,
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output led_al_a_c2m,
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output led_br_c_c2m,
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output led_br_a_c2m,
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output led_bl_c_c2m,
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output led_bl_a_c2m
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);
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// internal signals
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wire sys_ddr_cal_success;
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wire sys_ddr_cal_fail;
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wire sys_hps_resetn;
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wire sys_resetn_s;
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wire [ 63:0] gpio_i;
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wire [ 63:0] gpio_o;
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wire hps_emac_mdi_i_a;
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wire hps_emac_mdo_o_a;
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wire hps_emac_mdo_o_e_a;
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wire hps_emac_mdi_i_b;
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wire hps_emac_mdo_o_b;
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wire hps_emac_mdo_o_e_b;
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wire [ 3:0] mii_txd_extra_a;
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wire [ 3:0] mii_txd_extra_b;
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wire [ 1:0] mac_speed_0;
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wire [ 1:0] mac_speed_1;
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// assignments
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// port a - right led (activity/status)
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assign led_ar_c_c2m = led_0_a;
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assign led_ar_a_c2m = 1'b0;
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// port a - left led (speed mode): 10M=off, 100M=yellow
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assign led_al_c_c2m = mac_speed_0[0];
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assign led_al_a_c2m = mac_speed_0[1];
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// port b - right led (activity/status)
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assign led_br_c_c2m = led_0_b;
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assign led_br_a_c2m = 1'b0;
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// port a - left led (speed mode): 10M=off, 100M=yellow
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assign led_bl_c_c2m = mac_speed_1[1];
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assign led_bl_a_c2m = mac_speed_1[0];
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assign gpio_i[63:36] = gpio_o[63:36];
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assign gpio_i[35] = link_st_a;
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assign gpio_i[34] = link_st_b;
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assign gpio_i[33] = mii_crs_a;
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assign gpio_i[32] = mii_crs_b;
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// board stuff (max-v-u21)
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assign gpio_i[31:12] = gpio_o[31:12];
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assign gpio_i[ 3: 0] = gpio_o[ 3: 0];
|
||||
|
||||
assign gpio_i[11: 4] = gpio_bd_i;
|
||||
assign gpio_bd_o = gpio_o[3:0];
|
||||
|
||||
ALT_IOBUF md_iobuf_a (.i(hps_emac_mdo_o_a), .oe(hps_emac_mdo_o_e_a), .o(hps_emac_mdi_i_a), .io(mdio_fmc_a));
|
||||
ALT_IOBUF md_iobuf_b (.i(hps_emac_mdo_o_b), .oe(hps_emac_mdo_o_e_b), .o(hps_emac_mdi_i_b), .io(mdio_fmc_b));
|
||||
|
||||
// peripheral reset
|
||||
|
||||
assign sys_resetn_s = sys_resetn & sys_hps_resetn;
|
||||
assign reset_a = ~sys_resetn_s;
|
||||
assign reset_b = ~sys_resetn_s;
|
||||
|
||||
// instantiations
|
||||
|
||||
system_bd i_system_bd (
|
||||
.sys_clk_clk (sys_clk),
|
||||
.sys_gpio_bd_in_port (gpio_i[31:0]),
|
||||
.sys_gpio_bd_out_port (gpio_o[31:0]),
|
||||
.sys_gpio_in_export (gpio_i[63:32]),
|
||||
.sys_gpio_out_export (gpio_o[63:32]),
|
||||
.sys_hps_ddr_mem_ck (hps_ddr_clk_p),
|
||||
.sys_hps_ddr_mem_ck_n (hps_ddr_clk_n),
|
||||
.sys_hps_ddr_mem_a (hps_ddr_a),
|
||||
.sys_hps_ddr_mem_act_n (hps_ddr_act_n),
|
||||
.sys_hps_ddr_mem_ba (hps_ddr_ba),
|
||||
.sys_hps_ddr_mem_bg (hps_ddr_bg),
|
||||
.sys_hps_ddr_mem_cke (hps_ddr_cke),
|
||||
.sys_hps_ddr_mem_cs_n (hps_ddr_cs_n),
|
||||
.sys_hps_ddr_mem_odt (hps_ddr_odt),
|
||||
.sys_hps_ddr_mem_reset_n (hps_ddr_reset_n),
|
||||
.sys_hps_ddr_mem_par (hps_ddr_par),
|
||||
.sys_hps_ddr_mem_alert_n (hps_ddr_alert_n),
|
||||
.sys_hps_ddr_mem_dqs (hps_ddr_dqs_p),
|
||||
.sys_hps_ddr_mem_dqs_n (hps_ddr_dqs_n),
|
||||
.sys_hps_ddr_mem_dq (hps_ddr_dq),
|
||||
.sys_hps_ddr_mem_dbi_n (hps_ddr_dbi_n),
|
||||
.sys_hps_ddr_oct_oct_rzqin (hps_ddr_rzq),
|
||||
.sys_hps_ddr_ref_clk_clk (hps_ddr_ref_clk),
|
||||
.sys_hps_ddr_rstn_reset_n (sys_resetn),
|
||||
.sys_hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk),
|
||||
.sys_hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]),
|
||||
.sys_hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]),
|
||||
.sys_hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]),
|
||||
.sys_hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]),
|
||||
.sys_hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl),
|
||||
.sys_hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl),
|
||||
.sys_hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk),
|
||||
.sys_hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]),
|
||||
.sys_hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]),
|
||||
.sys_hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]),
|
||||
.sys_hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]),
|
||||
.sys_hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio),
|
||||
.sys_hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc),
|
||||
.sys_hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd),
|
||||
.sys_hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]),
|
||||
.sys_hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]),
|
||||
.sys_hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]),
|
||||
.sys_hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]),
|
||||
.sys_hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]),
|
||||
.sys_hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]),
|
||||
.sys_hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]),
|
||||
.sys_hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]),
|
||||
.sys_hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk),
|
||||
.sys_hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]),
|
||||
.sys_hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]),
|
||||
.sys_hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]),
|
||||
.sys_hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]),
|
||||
.sys_hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]),
|
||||
.sys_hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]),
|
||||
.sys_hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]),
|
||||
.sys_hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]),
|
||||
.sys_hps_io_hps_io_phery_usb0_CLK (hps_usb_clk),
|
||||
.sys_hps_io_hps_io_phery_usb0_STP (hps_usb_stp),
|
||||
.sys_hps_io_hps_io_phery_usb0_DIR (hps_usb_dir),
|
||||
.sys_hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt),
|
||||
.sys_hps_io_hps_io_phery_uart1_RX (hps_uart_rx),
|
||||
.sys_hps_io_hps_io_phery_uart1_TX (hps_uart_tx),
|
||||
.sys_hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda),
|
||||
.sys_hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl),
|
||||
.sys_hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]),
|
||||
.sys_hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]),
|
||||
.sys_hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]),
|
||||
.sys_hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]),
|
||||
.sys_hps_out_rstn_reset_n (sys_hps_resetn),
|
||||
.sys_hps_rstn_reset_n (sys_resetn),
|
||||
.sys_rstn_reset_n (sys_resetn_s),
|
||||
|
||||
.sys_hps_emac1_phy_mac_speed_o (mac_speed_0),
|
||||
.sys_hps_emac1_phy_txd_o ({mii_txd_extra_a,mii_txd_a}),
|
||||
.sys_hps_emac1_phy_txen_o (mii_tx_en_a),
|
||||
.sys_hps_emac1_phy_txer_o (),
|
||||
.sys_hps_emac1_phy_rxdv_i (mii_rx_dv_a),
|
||||
.sys_hps_emac1_phy_rxer_i (mii_rx_er_a),
|
||||
.sys_hps_emac1_phy_rxd_i ({4'h0,mii_rxd_a}),
|
||||
.sys_hps_emac1_phy_col_i (led_0_a),
|
||||
.sys_hps_emac1_phy_crs_i (mii_crs_a),
|
||||
.sys_hps_emac1_gmii_mdo_o (hps_emac_mdo_o_a),
|
||||
.sys_hps_emac1_gmii_mdo_o_e (hps_emac_mdo_o_e_a),
|
||||
.sys_hps_emac1_gmii_mdi_i (hps_emac_mdi_i_a),
|
||||
.sys_hps_emac1_md_clk_clk (mdc_fmc_a),
|
||||
.sys_hps_emac1_rx_clk_in_clk (mii_rx_clk_a),
|
||||
.sys_hps_emac1_tx_clk_in_clk (mii_tx_clk_a),
|
||||
|
||||
.sys_hps_emac2_phy_mac_speed_o (mac_speed_1),
|
||||
.sys_hps_emac2_phy_txd_o ({mii_txd_extra_b,mii_txd_b}),
|
||||
.sys_hps_emac2_phy_txen_o (mii_tx_en_b),
|
||||
.sys_hps_emac2_phy_txer_o (),
|
||||
.sys_hps_emac2_phy_rxdv_i (mii_rx_dv_b),
|
||||
.sys_hps_emac2_phy_rxer_i (mii_rx_er_b),
|
||||
.sys_hps_emac2_phy_rxd_i ({4'h0,mii_rxd_b}),
|
||||
.sys_hps_emac2_phy_col_i (led_0_b),
|
||||
.sys_hps_emac2_phy_crs_i (mii_crs_b),
|
||||
.sys_hps_emac2_gmii_mdo_o (hps_emac_mdo_o_b),
|
||||
.sys_hps_emac2_gmii_mdo_o_e (hps_emac_mdo_o_e_b),
|
||||
.sys_hps_emac2_gmii_mdi_i (hps_emac_mdi_i_b),
|
||||
.sys_hps_emac2_md_clk_clk (mdc_fmc_b),
|
||||
.sys_hps_emac2_rx_clk_in_clk (mii_rx_clk_b),
|
||||
.sys_hps_emac2_tx_clk_in_clk (mii_tx_clk_b)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
|
@ -1,34 +1,25 @@
|
|||
|
||||
# Instances and instance parameters
|
||||
|
||||
set_instance_parameter_value sys_hps {CLK_EMACA_SOURCE} {1}
|
||||
set_instance_parameter_value sys_hps {CLK_EMACB_SOURCE} {1}
|
||||
set_instance_parameter_value sys_hps {CLK_EMAC_PTP_SOURCE} {1}
|
||||
set_instance_parameter_value sys_hps {EMAC0_CLK} {250}
|
||||
set_instance_parameter_value sys_hps {EMAC0_Mode} {RMII_with_MDIO}
|
||||
set_instance_parameter_value sys_hps {EMAC0_PTP} {0}
|
||||
set_instance_parameter_value sys_hps {EMAC0_PinMuxing} {FPGA}
|
||||
set_instance_parameter_value sys_hps {EMAC0_SWITCH_Enable} {0}
|
||||
set_instance_parameter_value sys_hps {EMAC_PTP_REF_CLK} {100}
|
||||
set_instance_parameter_value sys_hps {EMAC1_CLK} {250}
|
||||
set_instance_parameter_value sys_hps {EMAC1_Mode} {RMII_with_MDIO}
|
||||
set_instance_parameter_value sys_hps {EMAC1_Mode} {RGMII_with_MDIO}
|
||||
set_instance_parameter_value sys_hps {EMAC1_PTP} {0}
|
||||
set_instance_parameter_value sys_hps {EMAC1_PinMuxing} {FPGA}
|
||||
set_instance_parameter_value sys_hps {EMAC1_SWITCH_Enable} {0}
|
||||
set_instance_parameter_value sys_hps {EMAC2_CLK} {250}
|
||||
set_instance_parameter_value sys_hps {EMAC2_Mode} {N/A}
|
||||
set_instance_parameter_value sys_hps {EMAC2_Mode} {RGMII_with_MDIO}
|
||||
set_instance_parameter_value sys_hps {EMAC2_PTP} {0}
|
||||
set_instance_parameter_value sys_hps {EMAC2_PinMuxing} {Unused}
|
||||
set_instance_parameter_value sys_hps {EMAC2_PinMuxing} {FPGA}
|
||||
set_instance_parameter_value sys_hps {EMAC2_SWITCH_Enable} {0}
|
||||
set_instance_parameter_value sys_hps {EMAC_PTP_REF_CLK} {100}
|
||||
set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK} {100}
|
||||
set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK} {2.5}
|
||||
set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK} {125}
|
||||
set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK} {2.5}
|
||||
set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_GTX_CLK} {125}
|
||||
set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_MD_CLK} {2.5}
|
||||
set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK} {100}
|
||||
set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK} {100}
|
||||
set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC0_CLK} {100}
|
||||
set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC1_CLK} {100}
|
||||
set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC2_CLK} {100}
|
||||
set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT} {100}
|
||||
|
|
@ -38,14 +29,6 @@ set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SC
|
|||
|
||||
|
||||
# exported interfaces
|
||||
add_interface sys_hps_emac0 conduit end
|
||||
set_interface_property sys_hps_emac0 EXPORT_OF sys_hps.emac0
|
||||
add_interface sys_hps_emac0_md_clk clock source
|
||||
set_interface_property sys_hps_emac0_md_clk EXPORT_OF sys_hps.emac0_md_clk
|
||||
add_interface sys_hps_emac0_rx_clk_in clock sink
|
||||
set_interface_property sys_hps_emac0_rx_clk_in EXPORT_OF sys_hps.emac0_rx_clk_in
|
||||
add_interface sys_hps_emac0_tx_clk_in clock sink
|
||||
set_interface_property sys_hps_emac0_tx_clk_in EXPORT_OF sys_hps.emac0_tx_clk_in
|
||||
add_interface sys_hps_emac1 conduit end
|
||||
set_interface_property sys_hps_emac1 EXPORT_OF sys_hps.emac1
|
||||
add_interface sys_hps_emac1_md_clk clock source
|
||||
|
|
@ -54,6 +37,14 @@ add_interface sys_hps_emac1_rx_clk_in clock sink
|
|||
set_interface_property sys_hps_emac1_rx_clk_in EXPORT_OF sys_hps.emac1_rx_clk_in
|
||||
add_interface sys_hps_emac1_tx_clk_in clock sink
|
||||
set_interface_property sys_hps_emac1_tx_clk_in EXPORT_OF sys_hps.emac1_tx_clk_in
|
||||
add_interface sys_hps_emac2 conduit end
|
||||
set_interface_property sys_hps_emac2 EXPORT_OF sys_hps.emac2
|
||||
add_interface sys_hps_emac2_md_clk clock source
|
||||
set_interface_property sys_hps_emac2_md_clk EXPORT_OF sys_hps.emac2_md_clk
|
||||
add_interface sys_hps_emac2_rx_clk_in clock sink
|
||||
set_interface_property sys_hps_emac2_rx_clk_in EXPORT_OF sys_hps.emac2_rx_clk_in
|
||||
add_interface sys_hps_emac2_tx_clk_in clock sink
|
||||
set_interface_property sys_hps_emac2_tx_clk_in EXPORT_OF sys_hps.emac2_tx_clk_in
|
||||
|
||||
# internal connections
|
||||
add_connection sys_clk.clk sys_hps.emac_ptp_ref_clock
|
||||
|
|
|
|||
Loading…
Reference in New Issue