diff --git a/projects/usrpe31x/Makefile b/projects/usrpe31x/Makefile new file mode 100644 index 000000000..b554b4b1f --- /dev/null +++ b/projects/usrpe31x/Makefile @@ -0,0 +1,66 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_constr.xdc +M_DEPS += system_bd.tcl +M_DEPS += ../scripts/adi_project.tcl +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_board.tcl +M_DEPS += ../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../library/axi_ad9361/axi_ad9361.xpr +M_DEPS += ../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../library/util_upack/util_upack.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib sdrstk.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../library/axi_ad9361 clean + make -C ../../library/axi_dmac clean + make -C ../../library/util_cpack clean + make -C ../../library/util_upack clean + + +sdrstk.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> sdrstk_vivado.log 2>&1 + + +lib: + make -C ../../library/axi_ad9361 + make -C ../../library/axi_dmac + make -C ../../library/util_cpack + make -C ../../library/util_upack + +#################################################################################### +#################################################################################### diff --git a/projects/usrpe31x/system_bd.tcl b/projects/usrpe31x/system_bd.tcl new file mode 100644 index 000000000..5ca44c4a5 --- /dev/null +++ b/projects/usrpe31x/system_bd.tcl @@ -0,0 +1,265 @@ +# create board design +# default ports + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr +create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io + +create_bd_port -dir O spi0_csn_2_o +create_bd_port -dir O spi0_csn_1_o +create_bd_port -dir O spi0_csn_0_o +create_bd_port -dir I spi0_csn_i +create_bd_port -dir I spi0_clk_i +create_bd_port -dir O spi0_clk_o +create_bd_port -dir I spi0_sdo_i +create_bd_port -dir O spi0_sdo_o +create_bd_port -dir I spi0_sdi_i + +create_bd_port -dir I -from 16 -to 0 gpio_i +create_bd_port -dir O -from 16 -to 0 gpio_o +create_bd_port -dir O -from 16 -to 0 gpio_t + +# interrupts + +create_bd_port -dir I -type intr ps_intr_00 +create_bd_port -dir I -type intr ps_intr_01 +create_bd_port -dir I -type intr ps_intr_02 +create_bd_port -dir I -type intr ps_intr_03 +create_bd_port -dir I -type intr ps_intr_04 +create_bd_port -dir I -type intr ps_intr_05 +create_bd_port -dir I -type intr ps_intr_06 +create_bd_port -dir I -type intr ps_intr_07 +create_bd_port -dir I -type intr ps_intr_08 +create_bd_port -dir I -type intr ps_intr_09 +create_bd_port -dir I -type intr ps_intr_10 +create_bd_port -dir I -type intr ps_intr_11 +create_bd_port -dir I -type intr ps_intr_12 +create_bd_port -dir I -type intr ps_intr_13 +create_bd_port -dir I -type intr ps_intr_14 +create_bd_port -dir I -type intr ps_intr_15 + +# instance: sys_ps7 + +set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7] + +# ps7 settings + +set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V}] $sys_ps7 +set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}] $sys_ps7 +set_property -dict [list CONFIG.PCW_PACKAGE_NAME {clg225}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {17}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UART1_UART1_IO {MIO 12 .. 13}] $sys_ps7 +set_property -dict [list CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 +set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 52}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7 + +# DDR MT41K256M16 HA-125 (32M, 16bit, 8banks) + +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.048}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.050}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.241}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.240}] $sys_ps7 + +set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc] +set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc + +set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] +set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen + +# system reset/clock definitions + +ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0 +ad_connect sys_200m_clk sys_ps7/FCLK_CLK1 +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N + +# interface connections + +ad_connect ddr sys_ps7/DDR +ad_connect gpio_i sys_ps7/GPIO_I +ad_connect gpio_o sys_ps7/GPIO_O +ad_connect gpio_t sys_ps7/GPIO_T +ad_connect fixed_io sys_ps7/FIXED_IO + +# spi connections + +ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O +ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O +ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O +ad_connect spi0_csn_i sys_ps7/SPI0_SS_I +ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I +ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O +ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I +ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O +ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I + +# interrupts + +ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P +ad_connect sys_concat_intc/In15 ps_intr_15 +ad_connect sys_concat_intc/In14 ps_intr_14 +ad_connect sys_concat_intc/In13 ps_intr_13 +ad_connect sys_concat_intc/In12 ps_intr_12 +ad_connect sys_concat_intc/In11 ps_intr_11 +ad_connect sys_concat_intc/In10 ps_intr_10 +ad_connect sys_concat_intc/In9 ps_intr_09 +ad_connect sys_concat_intc/In8 ps_intr_08 +ad_connect sys_concat_intc/In7 ps_intr_07 +ad_connect sys_concat_intc/In6 ps_intr_06 +ad_connect sys_concat_intc/In5 ps_intr_05 +ad_connect sys_concat_intc/In4 ps_intr_04 +ad_connect sys_concat_intc/In3 ps_intr_03 +ad_connect sys_concat_intc/In2 ps_intr_02 +ad_connect sys_concat_intc/In1 ps_intr_01 +ad_connect sys_concat_intc/In0 ps_intr_00 + +# iic + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main + +set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main] + +ad_connect iic_main axi_iic_main/iic +ad_cpu_interconnect 0x41600000 axi_iic_main +ad_cpu_interrupt ps-15 mb-15 axi_iic_main/iic2intc_irpt + +# ad9361 + +create_bd_port -dir I rx_clk_in +create_bd_port -dir I rx_frame_in +create_bd_port -dir I -from 11 -to 0 rx_data_in + +create_bd_port -dir O tx_clk_out +create_bd_port -dir O tx_frame_out +create_bd_port -dir O -from 11 -to 0 tx_data_out + +create_bd_port -dir O enable +create_bd_port -dir O txnrx +create_bd_port -dir I up_enable +create_bd_port -dir I up_txnrx + +# ad9361 core(s) + +set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361] +set_property -dict [list CONFIG.ID {0}] $axi_ad9361 +set_property -dict [list CONFIG.CMOS_OR_LVDS_N {1}] $axi_ad9361 + +set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {32}] $axi_ad9361_dac_dma + +set util_ad9361_dac_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9361_dac_upack] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9361_dac_upack +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_dac_upack + +set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $axi_ad9361_adc_dma + +set util_ad9361_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9361_adc_pack] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9361_adc_pack +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_adc_pack + +# connections + +ad_connect rx_clk_in axi_ad9361/rx_clk_in +ad_connect rx_frame_in axi_ad9361/rx_frame_in +ad_connect rx_data_in axi_ad9361/rx_data_in +ad_connect tx_clk_out axi_ad9361/tx_clk_out +ad_connect tx_frame_out axi_ad9361/tx_frame_out +ad_connect tx_data_out axi_ad9361/tx_data_out +ad_connect enable axi_ad9361/enable +ad_connect txnrx axi_ad9361/txnrx +ad_connect up_enable axi_ad9361/up_enable +ad_connect up_txnrx axi_ad9361/up_txnrx + +ad_connect axi_ad9361/tdd_sync GND +ad_connect sys_200m_clk axi_ad9361/delay_clk +ad_connect axi_ad9361/l_clk axi_ad9361/clk + +ad_connect axi_ad9361/l_clk util_ad9361_adc_pack/adc_clk +ad_connect axi_ad9361/rst util_ad9361_adc_pack/adc_rst +ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_pack/adc_enable_0 +ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_pack/adc_valid_0 +ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_pack/adc_data_0 +ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_pack/adc_enable_1 +ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_pack/adc_valid_1 +ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_pack/adc_data_1 +ad_connect axi_ad9361/l_clk axi_ad9361_adc_dma/fifo_wr_clk +ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en +ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync +ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din +ad_connect axi_ad9361_adc_dma/fifo_wr_overflow axi_ad9361/adc_dovf +ad_connect axi_ad9361/l_clk util_ad9361_dac_upack/dac_clk +ad_connect axi_ad9361/dac_enable_i0 util_ad9361_dac_upack/dac_enable_0 +ad_connect axi_ad9361/dac_valid_i0 util_ad9361_dac_upack/dac_valid_0 +ad_connect util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0 +ad_connect axi_ad9361/dac_enable_q0 util_ad9361_dac_upack/dac_enable_1 +ad_connect axi_ad9361/dac_valid_q0 util_ad9361_dac_upack/dac_valid_1 +ad_connect util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0 +ad_connect axi_ad9361/l_clk axi_ad9361_dac_dma/fifo_rd_clk +ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en +ad_connect axi_ad9361_dac_dma/fifo_rd_dout util_ad9361_dac_upack/dac_data +ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf +ad_connect axi_ad9361/dac_data_i1 GND +ad_connect axi_ad9361/dac_data_q1 GND + +# interconnects + +ad_cpu_interconnect 0x79020000 axi_ad9361 +ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma +ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma +ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi +ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi +ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn +ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn + +# interrupts + +ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq +ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq + + diff --git a/projects/usrpe31x/system_constr.xdc b/projects/usrpe31x/system_constr.xdc new file mode 100644 index 000000000..d41a6f328 --- /dev/null +++ b/projects/usrpe31x/system_constr.xdc @@ -0,0 +1,202 @@ +# constraints +# ad9361 (SWAP == 0x1) + +set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18 } [get_ports rx_clk_in] +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18 } [get_ports rx_frame_in] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[0]] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[1]] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[2]] +set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[3]] +set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[4]] +set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[5]] +set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[6]] +set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[7]] +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[8]] +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[9]] +set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[10]] +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[11]] + +set_property -dict {PACKAGE_PIN P10 IOSTANDARD LVCMOS18} [get_ports tx_clk_out] +set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS18} [get_ports tx_frame_out] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]] +set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]] +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]] +set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]] +set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]] +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]] +set_property -dict {PACKAGE_PIN P13 IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]] +set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]] +set_property -dict {PACKAGE_PIN M9 IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]] +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]] +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]] + +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] +set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]] +set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]] +set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]] +set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]] +set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]] +set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]] + +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]] +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]] +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]] +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]] + +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] +set_property -dict {PACKAGE_PIN P9 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] + +set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports enable] +set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports txnrx] + +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_scl] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_sda] + +set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn] +set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports spi_clk] +set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports spi_mosi] +set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports spi_miso] + +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports gpio_bd] +set_property -dict {PACKAGE_PIN P8 IOSTANDARD LVCMOS18} [get_ports clk_out] + +create_clock -name rx_clk -period 16 [get_ports rx_clk_in] + +# probably gone in 2016.4 + +create_clock -name clk_fpga_0 -period 10 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]"] +create_clock -name clk_fpga_1 -period 5 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]"] + +set_input_jitter clk_fpga_0 0.3 +set_input_jitter clk_fpga_1 0.15 + +set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_mio*] +set_property SLEW SLOW [get_ports *fixed_io_mio*] +set_property DRIVE 8 [get_ports *fixed_io_mio*] +set_property -dict {PACKAGE_PIN D8 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 0]] +set_property -dict {PACKAGE_PIN A5 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 1]] +set_property -dict {PACKAGE_PIN A8 } [get_ports fixed_io_mio[ 2]] +set_property -dict {PACKAGE_PIN A7 } [get_ports fixed_io_mio[ 3]] +set_property -dict {PACKAGE_PIN C8 } [get_ports fixed_io_mio[ 4]] +set_property -dict {PACKAGE_PIN A9 } [get_ports fixed_io_mio[ 5]] +set_property -dict {PACKAGE_PIN A10 } [get_ports fixed_io_mio[ 6]] +set_property -dict {PACKAGE_PIN D9 } [get_ports fixed_io_mio[ 7]] +set_property -dict {PACKAGE_PIN B6 } [get_ports fixed_io_mio[ 8]] +set_property -dict {PACKAGE_PIN B5 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 9]] +set_property -dict {PACKAGE_PIN D6 PULLTYPE PULLUP} [get_ports fixed_io_mio[10]] +set_property -dict {PACKAGE_PIN B10 PULLTYPE PULLUP} [get_ports fixed_io_mio[11]] +set_property -dict {PACKAGE_PIN B7 PULLTYPE PULLUP} [get_ports fixed_io_mio[12]] +set_property -dict {PACKAGE_PIN C6 PULLTYPE PULLUP} [get_ports fixed_io_mio[13]] +set_property -dict {PACKAGE_PIN B9 PULLTYPE PULLUP} [get_ports fixed_io_mio[14]] +set_property -dict {PACKAGE_PIN D10 PULLTYPE PULLUP} [get_ports fixed_io_mio[15]] +set_property -dict {PACKAGE_PIN A15 PULLTYPE PULLUP} [get_ports fixed_io_mio[16]] +set_property -dict {PACKAGE_PIN D11 PULLTYPE PULLUP} [get_ports fixed_io_mio[17]] +set_property -dict {PACKAGE_PIN B15 PULLTYPE PULLUP} [get_ports fixed_io_mio[18]] +set_property -dict {PACKAGE_PIN C12 PULLTYPE PULLUP} [get_ports fixed_io_mio[19]] +set_property -dict {PACKAGE_PIN E15 PULLTYPE PULLUP} [get_ports fixed_io_mio[20]] +set_property -dict {PACKAGE_PIN C11 PULLTYPE PULLUP} [get_ports fixed_io_mio[21]] +set_property -dict {PACKAGE_PIN D15 PULLTYPE PULLUP} [get_ports fixed_io_mio[22]] +set_property -dict {PACKAGE_PIN A14 PULLTYPE PULLUP} [get_ports fixed_io_mio[23]] +set_property -dict {PACKAGE_PIN B14 PULLTYPE PULLUP} [get_ports fixed_io_mio[24]] +set_property -dict {PACKAGE_PIN C14 PULLTYPE PULLUP} [get_ports fixed_io_mio[25]] +set_property -dict {PACKAGE_PIN A13 PULLTYPE PULLUP} [get_ports fixed_io_mio[26]] +set_property -dict {PACKAGE_PIN D14 PULLTYPE PULLUP} [get_ports fixed_io_mio[27]] +set_property -dict {PACKAGE_PIN B12 PULLTYPE PULLUP} [get_ports fixed_io_mio[28]] +set_property -dict {PACKAGE_PIN D13 PULLTYPE PULLUP} [get_ports fixed_io_mio[29]] +set_property -dict {PACKAGE_PIN A12 PULLTYPE PULLUP} [get_ports fixed_io_mio[30]] +set_property -dict {PACKAGE_PIN C13 PULLTYPE PULLUP} [get_ports fixed_io_mio[31]] + +set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_ps*] +set_property SLEW SLOW [get_ports *fixed_io_ps*] +set_property DRIVE 8 [get_ports *fixed_io_ps*] +set_property PACKAGE_PIN C7 [get_ports fixed_io_ps_clk] +set_property PACKAGE_PIN C9 [get_ports fixed_io_ps_porb] + +set_property IOSTANDARD SSTL15_T_DCI [get_ports *fixed_io_ddr_vr*] +set_property SLEW FAST [get_ports *fixed_io_ddr_vr*] +set_property PACKAGE_PIN H3 [get_ports fixed_io_ddr_vrp] +set_property PACKAGE_PIN J3 [get_ports fixed_io_ddr_vrn] + +set_property IOSTANDARD DIFF_SSTL15 [get_ports *ddr_ck*] +set_property SLEW FAST [get_ports *ddr_ck*] +set_property PACKAGE_PIN N3 [get_ports ddr_ck_p] +set_property PACKAGE_PIN N2 [get_ports ddr_ck_n] + +set_property IOSTANDARD SSTL15 [get_ports *ddr_addr*] +set_property SLEW SLOW [get_ports *ddr_addr*] +set_property PACKAGE_PIN P1 [get_ports ddr_addr[0]] +set_property PACKAGE_PIN N1 [get_ports ddr_addr[1]] +set_property PACKAGE_PIN M1 [get_ports ddr_addr[2]] +set_property PACKAGE_PIN M4 [get_ports ddr_addr[3]] +set_property PACKAGE_PIN P3 [get_ports ddr_addr[4]] +set_property PACKAGE_PIN P4 [get_ports ddr_addr[5]] +set_property PACKAGE_PIN P5 [get_ports ddr_addr[6]] +set_property PACKAGE_PIN M5 [get_ports ddr_addr[7]] +set_property PACKAGE_PIN P6 [get_ports ddr_addr[8]] +set_property PACKAGE_PIN N4 [get_ports ddr_addr[9]] +set_property PACKAGE_PIN J1 [get_ports ddr_addr[10]] +set_property PACKAGE_PIN L2 [get_ports ddr_addr[11]] +set_property PACKAGE_PIN M2 [get_ports ddr_addr[12]] +set_property PACKAGE_PIN K2 [get_ports ddr_addr[13]] +set_property PACKAGE_PIN K1 [get_ports ddr_addr[14]] + +set_property IOSTANDARD SSTL15 [get_ports *ddr_ba*] +set_property SLEW SLOW [get_ports *ddr_ba*] +set_property PACKAGE_PIN M6 [get_ports ddr_ba[0]] +set_property PACKAGE_PIN R1 [get_ports ddr_ba[1]] +set_property PACKAGE_PIN N6 [get_ports ddr_ba[2]] + +set_property IOSTANDARD SSTL15 [get_ports ddr_reset_n] +set_property SLEW FAST [get_ports ddr_reset_n] +set_property PACKAGE_PIN L4 [get_ports ddr_reset_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_cs_n] +set_property SLEW SLOW [get_ports ddr_cs_n] +set_property PACKAGE_PIN R2 [get_ports ddr_cs_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_ras_n] +set_property SLEW SLOW [get_ports ddr_ras_n] +set_property PACKAGE_PIN R6 [get_ports ddr_ras_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_cas_n] +set_property SLEW SLOW [get_ports ddr_cas_n] +set_property PACKAGE_PIN R5 [get_ports ddr_cas_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_we_n] +set_property SLEW SLOW [get_ports ddr_we_n] +set_property PACKAGE_PIN R3 [get_ports ddr_we_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_cke] +set_property SLEW SLOW [get_ports ddr_cke] +set_property PACKAGE_PIN L3 [get_ports ddr_cke] +set_property IOSTANDARD SSTL15 [get_ports ddr_odt] +set_property SLEW SLOW [get_ports ddr_odt] +set_property PACKAGE_PIN K3 [get_ports ddr_odt] + +set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dq[*]] +set_property SLEW FAST [get_ports *ddr_dq[*]] +set_property PACKAGE_PIN D4 [get_ports ddr_dq[0]] +set_property PACKAGE_PIN A2 [get_ports ddr_dq[1]] +set_property PACKAGE_PIN C4 [get_ports ddr_dq[2]] +set_property PACKAGE_PIN C1 [get_ports ddr_dq[3]] +set_property PACKAGE_PIN B4 [get_ports ddr_dq[4]] +set_property PACKAGE_PIN A4 [get_ports ddr_dq[5]] +set_property PACKAGE_PIN C3 [get_ports ddr_dq[6]] +set_property PACKAGE_PIN A3 [get_ports ddr_dq[7]] +set_property PACKAGE_PIN E1 [get_ports ddr_dq[8]] +set_property PACKAGE_PIN D1 [get_ports ddr_dq[9]] +set_property PACKAGE_PIN E2 [get_ports ddr_dq[10]] +set_property PACKAGE_PIN E3 [get_ports ddr_dq[11]] +set_property PACKAGE_PIN F3 [get_ports ddr_dq[12]] +set_property PACKAGE_PIN G1 [get_ports ddr_dq[13]] +set_property PACKAGE_PIN H1 [get_ports ddr_dq[14]] +set_property PACKAGE_PIN H2 [get_ports ddr_dq[15]] +set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dm[*]] +set_property SLEW FAST [get_ports *ddr_dm[*]] +set_property PACKAGE_PIN B1 [get_ports ddr_dm[0]] +set_property PACKAGE_PIN D3 [get_ports ddr_dm[1]] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports *ddr_dqs*] +set_property SLEW FAST [get_ports *ddr_dqs*] +set_property PACKAGE_PIN C2 [get_ports ddr_dqs_p[0]] +set_property PACKAGE_PIN B2 [get_ports ddr_dqs_n[0]] +set_property PACKAGE_PIN G2 [get_ports ddr_dqs_p[1]] +set_property PACKAGE_PIN F2 [get_ports ddr_dqs_n[1]] + + diff --git a/projects/usrpe31x/system_project.tcl b/projects/usrpe31x/system_project.tcl new file mode 100644 index 000000000..4586ed0c6 --- /dev/null +++ b/projects/usrpe31x/system_project.tcl @@ -0,0 +1,16 @@ + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z020clg484-1" +adi_project_create usrpe31x + +adi_project_files usrpe31x [list \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] + +adi_project_run usrpe31x + + diff --git a/projects/usrpe31x/system_top.v b/projects/usrpe31x/system_top.v new file mode 100644 index 000000000..c74269645 --- /dev/null +++ b/projects/usrpe31x/system_top.v @@ -0,0 +1,172 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 1:0] ddr_dm, + inout [15:0] ddr_dq, + inout [ 1:0] ddr_dqs_n, + inout [ 1:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [31:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout iic_scl, + inout iic_sda, + + inout gpio_bd, + + input rx_clk_in, + input rx_frame_in, + input [11:0] rx_data_in, + output tx_clk_out, + output tx_frame_out, + output [11:0] tx_data_out, + + output enable, + output txnrx, + input clk_out, + + inout gpio_resetb, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso); + + // internal signals + + wire [16:0] gpio_i; + wire [16:0] gpio_o; + wire [16:0] gpio_t; + + // instantiations + + ad_iobuf #(.DATA_WIDTH(15)) i_iobuf ( + .dio_t (gpio_t[14:0]), + .dio_i (gpio_o[14:0]), + .dio_o (gpio_i[14:0]), + .dio_p ({ gpio_bd, // 14:14 + gpio_resetb, // 13:13 + gpio_en_agc, // 12:12 + gpio_ctl, // 11: 8 + gpio_status})); // 7: 0 + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .ps_intr_14 (1'b0), + .rx_clk_in (rx_clk_in), + .rx_data_in (rx_data_in), + .rx_frame_in (rx_frame_in), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .tx_clk_out (tx_clk_out), + .tx_data_out (tx_data_out), + .tx_frame_out (tx_frame_out), + .txnrx (txnrx), + .up_enable (gpio_o[15]), + .up_txnrx (gpio_o[16])); + +endmodule + +// *************************************************************************** +// ***************************************************************************