dac/adc-rst: common ad-rst instance
parent
0e587dd955
commit
483e375910
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@ -156,7 +156,7 @@ module up_adc_common (
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// internal registers
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// internal registers
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reg up_preset = 'd0;
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reg up_core_preset = 'd0;
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reg up_mmcm_preset = 'd0;
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reg up_mmcm_preset = 'd0;
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reg up_wack = 'd0;
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reg up_wack = 'd0;
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reg [31:0] up_scratch = 'd0;
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reg [31:0] up_scratch = 'd0;
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@ -201,7 +201,7 @@ module up_adc_common (
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always @(negedge up_rstn or posedge up_clk) begin
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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if (up_rstn == 0) begin
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up_preset <= 1'd1;
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up_core_preset <= 1'd1;
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up_mmcm_preset <= 1'd1;
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up_mmcm_preset <= 1'd1;
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up_wack <= 'd0;
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up_wack <= 'd0;
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up_scratch <= 'd0;
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up_scratch <= 'd0;
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@ -223,7 +223,7 @@ module up_adc_common (
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up_adc_gpio_out <= 'd0;
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up_adc_gpio_out <= 'd0;
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up_adc_start_code <= 'd0;
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up_adc_start_code <= 'd0;
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end else begin
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end else begin
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up_preset <= 1'd0;
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up_core_preset <= 1'd0;
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up_mmcm_preset <= ~up_mmcm_resetn;
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up_mmcm_preset <= ~up_mmcm_resetn;
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up_wack <= up_wreq_s;
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
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@ -325,7 +325,7 @@ module up_adc_common (
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// resets
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// resets
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ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset), .clk(up_clk), .rst(mmcm_rst));
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ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset), .clk(up_clk), .rst(mmcm_rst));
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ad_rst i_adc_rst_reg (.preset(up_preset), .clk(adc_clk), .rst(adc_rst));
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ad_rst i_core_rst_reg (.preset(up_core_preset), .clk(adc_clk), .rst(adc_rst));
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// adc control & status
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// adc control & status
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