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axi_dacfifo: Fix port width at axi_dacfifo_wr

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Istvan Csomortani 2017-07-14 16:47:34 +03:00
parent 711cb66985
commit 4832bc1a0c
1 changed files with 1 additions and 1 deletions
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library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
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@ -82,7 +82,7 @@ module axi_dacfifo_wr #(
output reg [31:0] axi_awaddr, output reg [31:0] axi_awaddr,
input axi_awready, input axi_awready,
output axi_wvalid, output axi_wvalid,
output [((AXI_DATA_WIDTH/8)-1):0] axi_wdata, output [(AXI_DATA_WIDTH-1):0] axi_wdata,
output [((AXI_DATA_WIDTH/8)-1):0] axi_wstrb, output [((AXI_DATA_WIDTH/8)-1):0] axi_wstrb,
output axi_wlast, output axi_wlast,
output [ 3:0] axi_wuser, output [ 3:0] axi_wuser,