axi_dacfifo: Fix port width at axi_dacfifo_wr

2017-07-14 16:47:34 +03:00 · 2017-07-14 16:47:34 +03:00 · 4832bc1a0c
parent 711cb66985
commit 4832bc1a0c
1 changed files with 1 additions and 1 deletions
--- a/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
@ -82,7 +82,7 @@ module axi_dacfifo_wr #(
  output  reg [31:0]      axi_awaddr,
  input                   axi_awready,
  output                  axi_wvalid,
-  output      [((AXI_DATA_WIDTH/8)-1):0]  axi_wdata,
+  output      [(AXI_DATA_WIDTH-1):0]      axi_wdata,
  output      [((AXI_DATA_WIDTH/8)-1):0]  axi_wstrb,
  output                  axi_wlast,
  output      [ 3:0]      axi_wuser,