ad7134_fmc: Switch offload trigger to falling ODR

projects/ad7134_fmc/common/ad7134_bd.tcl

@@ -10,6 +10,7 @@ create_bd_cell -type hier dual_ad7134
 current_bd_instance /dual_ad7134
 
   create_bd_pin -dir I -type clk clk
+  create_bd_pin -dir I -type clk spi_clk
   create_bd_pin -dir I -type rst resetn
   create_bd_pin -dir I odr
   create_bd_pin -dir O irq
@@ -31,11 +32,13 @@ current_bd_instance /dual_ad7134
   ad_ip_parameter axi CONFIG.DATA_WIDTH $data_width
   ad_ip_parameter axi CONFIG.NUM_OF_SDI $adc_num_of_channels
   ad_ip_parameter axi CONFIG.NUM_OFFLOAD 1
+  ad_ip_parameter axi CONFIG.ASYNC_SPI_CLK 1
 
   ad_ip_instance spi_engine_offload offload
   ad_ip_parameter offload CONFIG.DATA_WIDTH $data_width
   ad_ip_parameter offload CONFIG.NUM_OF_SDI $adc_num_of_channels
   ad_ip_parameter offload CONFIG.ASYNC_TRIG 1
+  ad_ip_parameter offload CONFIG.ASYNC_SPI_CLK 1
 
   ad_ip_instance spi_engine_interconnect interconnect
   ad_ip_parameter interconnect CONFIG.DATA_WIDTH $data_width
@@ -50,12 +53,12 @@ current_bd_instance /dual_ad7134
 
   ad_connect execution/spi m_spi
 
-  ad_connect clk offload/spi_clk
+  ad_connect spi_clk offload/spi_clk
-  ad_connect clk offload/ctrl_clk
+  ad_connect spi_clk offload/ctrl_clk
-  ad_connect clk execution/clk
+  ad_connect spi_clk execution/clk
   ad_connect clk axi/s_axi_aclk
-  ad_connect clk axi/spi_clk
+  ad_connect spi_clk axi/spi_clk
-  ad_connect clk interconnect/clk
+  ad_connect spi_clk interconnect/clk
 
   ad_connect axi/spi_resetn offload/spi_resetn
   ad_connect axi/spi_resetn execution/resetn
@@ -68,6 +71,13 @@ current_bd_instance /dual_ad7134
 
 current_bd_instance /
 
+# clkgen
+
+ad_ip_instance axi_clkgen axi_ad7134_clkgen
+ad_ip_parameter axi_ad7134_clkgen CONFIG.VCO_DIV 5
+ad_ip_parameter axi_ad7134_clkgen CONFIG.VCO_MUL 48
+ad_ip_parameter axi_ad7134_clkgen CONFIG.CLK0_DIV 10
+
 # dma to receive data stream
 
 ad_ip_instance axi_dmac axi_ad7134_dma
@@ -87,9 +97,22 @@ ad_ip_instance axi_pwm_gen odr_generator
 ad_ip_parameter odr_generator CONFIG.N_PWMS 1
 ad_ip_parameter odr_generator CONFIG.PULSE_0_PERIOD 10000
 ad_ip_parameter odr_generator CONFIG.PULSE_0_WIDTH 4
+ad_ip_parameter odr_generator CONFIG.ASYNC_CLK_EN 0
+
+create_bd_cell -type module -reference sync_bits busy_sync
+create_bd_cell -type module -reference ad_edge_detect busy_capture
+set_property -dict [list CONFIG.EDGE 1] [get_bd_cells busy_capture]
 
 ad_connect odr_generator/pwm_0 ad713x_odr
-ad_connect $sys_cpu_clk odr_generator/ext_clk
+
+ad_connect axi_ad7134_clkgen/clk_0 busy_capture/clk
+ad_connect axi_ad7134_clkgen/clk_0 busy_sync/out_clk
+ad_connect busy_capture/rst GND
+ad_connect dual_ad7134/axi/spi_resetn busy_sync/out_resetn
+
+ad_connect ad713x_odr busy_sync/in_bits
+ad_connect busy_sync/out_bits busy_capture/signal_in
+ad_connect busy_capture/signal_out dual_ad7134/odr
 
 # sdpclk clock generator - default clk0_out is 50 MHz
 
@@ -99,14 +122,15 @@ ad_ip_parameter axi_sdp_clkgen CONFIG.VCO_MUL 12
 ad_ip_parameter axi_sdp_clkgen CONFIG.VCO_DIV 2
 ad_ip_parameter axi_sdp_clkgen CONFIG.CLK0_DIV 12
 
+ad_connect  axi_ad7134_clkgen/clk_0 dual_ad7134/spi_clk
+ad_connect  sys_cpu_clk axi_ad7134_clkgen/clk 
 ad_connect  sys_cpu_clk dual_ad7134/clk
-ad_connect  sys_cpu_clk axi_ad7134_dma/s_axis_aclk
+ad_connect  axi_ad7134_clkgen/clk_0 axi_ad7134_dma/s_axis_aclk
 ad_connect  sys_cpu_clk axi_sdp_clkgen/clk
 ad_connect  sys_cpu_resetn dual_ad7134/resetn
 ad_connect  sys_cpu_resetn axi_ad7134_dma/m_dest_axi_aresetn
 
 ad_connect  dual_ad7134/m_spi ad713x_di
-ad_connect  dual_ad7134/odr ad713x_odr
 ad_connect  axi_ad7134_dma/s_axis dual_ad7134/M_AXIS_SAMPLE
 ad_connect  ad713x_sdpclk axi_sdp_clkgen/clk_0
 
@@ -114,6 +138,7 @@ ad_cpu_interconnect 0x44a00000 dual_ad7134/axi
 ad_cpu_interconnect 0x44a30000 axi_ad7134_dma
 ad_cpu_interconnect 0x44a40000 axi_sdp_clkgen
 ad_cpu_interconnect 0x44b00000 odr_generator
+ad_cpu_interconnect 0x44b10000 axi_ad7134_clkgen
 
 ad_cpu_interrupt "ps-13" "mb-13" axi_ad7134_dma/irq
 ad_cpu_interrupt "ps-12" "mb-12" dual_ad7134/irq

projects/ad7134_fmc/zed/Makefile

@@ -10,13 +10,15 @@ M_DEPS += ../common/ad7134_bd.tcl
 M_DEPS += ../../scripts/adi_pd.tcl
 M_DEPS += ../../common/zed/zed_system_constr.xdc
 M_DEPS += ../../common/zed/zed_system_bd.tcl
+M_DEPS += ../../../library/util_cdc/sync_bits.v
 M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/common/ad_edge_detect.v
 
 LIB_DEPS += axi_clkgen
-LIB_DEPS += axi_pwm_gen
 LIB_DEPS += axi_dmac
 LIB_DEPS += axi_hdmi_tx
 LIB_DEPS += axi_i2s_adi
+LIB_DEPS += axi_pwm_gen
 LIB_DEPS += axi_spdif_tx
 LIB_DEPS += axi_sysid
 LIB_DEPS += spi_engine/axi_spi_engine

projects/ad7134_fmc/zed/system_bd.tcl

@@ -2,6 +2,11 @@
 source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
 source $ad_hdl_dir/projects/scripts/adi_pd.tcl
 
+adi_project_files ad7134_fmc_zed [list \
+  "$ad_hdl_dir/library/common/ad_edge_detect.v" \
+  "$ad_hdl_dir/library/util_cdc/sync_bits.v" \
+]
+
 #system ID
 ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
 ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
@@ -17,4 +22,5 @@ set adc_resolution 24
 
 set adc_num_of_channels 8
 
+
 source ../common/ad7134_bd.tcl

projects/ad7134_fmc/zed/system_constr.xdc

@@ -45,3 +45,5 @@ set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS25} [get_ports ad713x_dclkm
 
 set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad713x_sdpclk]        ; ## FMC_LPC_LA01_CC_N
 
+set_false_path -to [get_pins -hierarchical * -filter {NAME=~*busy_sync/inst/cdc_sync_stage1_reg[0]/D}]
+