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axi_ad9361: Bring up the tdd_enable bit 

This line will be the selection bit of the GPIO/TDD_FSM mux for ENABLE/TXNRX control
main
Istvan Csomortani 2015-07-01 13:52:00 +03:00
parent 499357a65a
commit 4744fca18e
2 changed files with 559 additions and 549 deletions
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8
library/axi_ad9361/axi_ad9361.v
View File

@ -72,6 +72,7 @@ module axi_ad9361 (
l_clk,
clk,
rst,
// dma interface
@ -107,6 +108,8 @@ module axi_ad9361 (
dac_dunf,
dac_r1_mode,
tdd_enable,
enable,
txnrx,
@ -185,6 +188,7 @@ module axi_ad9361 (
output l_clk;
input clk;
output rst;
// dma interface
@ -220,6 +224,8 @@ module axi_ad9361 (
input dac_dunf;
output dac_r1_mode;
output tdd_enable;
output enable;
output txnrx;
@ -266,7 +272,6 @@ module axi_ad9361 (
// internal clocks and resets
wire rst;
wire up_clk;
wire up_rstn;
wire delay_rst;
@ -396,6 +401,7 @@ module axi_ad9361 (
.tdd_tx_vco_en(tdd_tx_vco_en_s),
.tdd_rx_rf_en(tdd_rx_rf_en_s),
.tdd_tx_rf_en(tdd_tx_rf_en_s),
.tdd_enable (tdd_enable),
.tdd_status(tdd_status_s),
.tx_valid_i0(dac_valid_i0_s),
.tx_valid_q0(dac_valid_q0_s),

4
library/axi_ad9361/axi_ad9361_tdd.v
View File

@ -55,6 +55,7 @@ module axi_ad9361_tdd (
// status signal
tdd_enable,
tdd_status,
// tx data flow control
@ -95,6 +96,7 @@ module axi_ad9361_tdd (
output tdd_rx_rf_en;
output tdd_tx_rf_en;
output tdd_enable;
input [ 7:0] tdd_status;
// tx data flow control
@ -169,6 +171,8 @@ module axi_ad9361_tdd (
assign tdd_tx_valid_i1 = (tdd_enable_s == 1'b1) ? (tx_valid_i1 & tdd_tx_dp_en_s) : tx_valid_i1;
assign tdd_tx_valid_q1 = (tdd_enable_s == 1'b1) ? (tx_valid_q1 & tdd_tx_dp_en_s) : tx_valid_q1;
assign tdd_enable = tdd_enable_s;
// instantiations
up_tdd_cntrl i_up_tdd_cntrl(