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adrv9009/qsys: input pipline active for jesd204_rx and jesd204_rx_os

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Istvan Csomortani 2020-02-05 17:05:06 +00:00 committed by István Csomortáni
parent 256593623c
commit 46b6bf8f8a
1 changed files with 2 additions and 0 deletions
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projects/adrv9009/common/adrv9009_qsys.tcl
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@ -58,6 +58,7 @@ set_instance_parameter_value adrv9009_rx_jesd204 {SOFT_PCS} {true}
set_instance_parameter_value adrv9009_rx_jesd204 {LANE_RATE} {9830.4}
set_instance_parameter_value adrv9009_rx_jesd204 {REFCLK_FREQUENCY} {245.76}
set_instance_parameter_value adrv9009_rx_jesd204 {NUM_OF_LANES} $RX_NUM_OF_LANES
set_instance_parameter_value adrv9009_rx_jesd204 {INPUT_PIPELINE_STAGES} {1}
add_connection sys_clk.clk adrv9009_rx_jesd204.sys_clk
add_connection sys_clk.clk_reset adrv9009_rx_jesd204.sys_resetn
@ -79,6 +80,7 @@ set_instance_parameter_value adrv9009_rx_os_jesd204 {SOFT_PCS} {true}
set_instance_parameter_value adrv9009_rx_os_jesd204 {LANE_RATE} {9830.4}
set_instance_parameter_value adrv9009_rx_os_jesd204 {REFCLK_FREQUENCY} {245.76}
set_instance_parameter_value adrv9009_rx_os_jesd204 {NUM_OF_LANES} $RX_OS_NUM_OF_LANES
set_instance_parameter_value adrv9009_rx_os_jesd204 {INPUT_PIPELINE_STAGES} {1}
add_connection sys_clk.clk adrv9009_rx_os_jesd204.sys_clk
add_connection sys_clk.clk_reset adrv9009_rx_os_jesd204.sys_resetn