util_wfifo: Changed some reset for several registers from asynchronous to synchronous for better integration with the FIFO
parent
70cea5b14e
commit
46808c4c41
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@ -306,13 +306,19 @@ module util_wfifo (
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if (dout_rstn == 1'b0) begin
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if (dout_rstn == 1'b0) begin
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dout_enable_m <= 'd0;
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dout_enable_m <= 'd0;
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dout_enable <= 'd0;
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dout_enable <= 'd0;
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end else begin
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dout_enable_m <= din_enable;
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dout_enable <= dout_enable_m;
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end
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end
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always @(posedge dout_clk) begin
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if (dout_rstn == 1'b0) begin
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dout_rd <= 'd0;
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dout_rd <= 'd0;
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dout_rd_d <= 'd0;
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dout_rd_d <= 'd0;
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dout_rdata_d <= 'd0;
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dout_rdata_d <= 'd0;
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dout_raddr <= 'd0;
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dout_raddr <= 'd0;
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end else begin
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end else begin
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dout_enable_m <= din_enable;
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dout_enable <= dout_enable_m;
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dout_rd <= dout_rd_s;
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dout_rd <= dout_rd_s;
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dout_rd_d <= dout_rd;
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dout_rd_d <= dout_rd;
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dout_rdata_d <= dout_rdata_s;
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dout_rdata_d <= dout_rdata_s;
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