adrv9371x/a10soc: Misc changes for being able to run Linux
dbogdan
parent
e754f0a46a
commit
4658686ae1
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@ -41,6 +41,22 @@
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type = "String";
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}
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}
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element adrv9371x.avl_gpio_i
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{
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datum baseAddress
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{
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value = "222464";
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type = "String";
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}
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}
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element adrv9371x.avl_gpio_o
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{
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datum baseAddress
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{
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value = "222720";
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type = "String";
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}
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}
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element adrv9371x.avl_rx_jesd
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{
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datum baseAddress
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@ -57,6 +73,14 @@
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type = "String";
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}
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}
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element adrv9371x.avl_spi
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{
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datum baseAddress
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{
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value = "222976";
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type = "String";
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}
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}
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element adrv9371x.avl_tx_jesd
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{
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datum baseAddress
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@ -375,6 +399,8 @@
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<parameter name="useTestBenchNamingPattern" value="false" />
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<instanceScript></instanceScript>
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<interface name="gpio" internal="adrv9371x.ad9371_gpio" type="conduit" dir="end" />
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<interface name="gpio_i" internal="adrv9371x.gpio_i" type="conduit" dir="end" />
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<interface name="gpio_o" internal="adrv9371x.gpio_o" type="conduit" dir="end" />
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<interface name="hps_ddr" internal="a10soc.hps_ddr" type="conduit" dir="end" />
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<interface
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name="hps_ddr_oct"
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@ -386,7 +412,7 @@
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internal="a10soc.hps_ddr_ref_clk"
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type="clock"
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dir="end" />
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<interface name="hps_gpio" internal="a10soc.hps_gpio" type="conduit" dir="end" />
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<interface name="hps_gpio" internal="a10soc.hps_gpio" />
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<interface name="hps_io" internal="a10soc.hps_io" type="conduit" dir="end" />
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<interface name="hps_spi0" internal="a10soc.hps_spi0" type="conduit" dir="end" />
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<interface
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@ -427,6 +453,7 @@
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internal="adrv9371x.rx_sysref"
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type="conduit"
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dir="end" />
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<interface name="spi" internal="adrv9371x.spi" type="conduit" dir="end" />
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<interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
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<interface
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name="sys_reset"
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@ -448,12 +475,12 @@
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<parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_DOMAIN" value="1" />
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<parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_RATE" value="0" />
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<parameter name="AUTO_HPS_DDR_REF_CLK_RESET_DOMAIN" value="1" />
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<parameter name="AUTO_HPS_IRQ0_INTERRUPTS_USED" value="15" />
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<parameter name="AUTO_HPS_IRQ0_INTERRUPTS_USED" value="31" />
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<parameter name="AUTO_HPS_IRQ1_INTERRUPTS_USED" value="0" />
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<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
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<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
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<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
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<parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='adrv9371x_axi_os_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='adrv9371x_axi_jesd_xcvr.s_axi' start='0x10000' end='0x20000' /><slave name='adrv9371x_axi_dac_dma.s_axi' start='0x20000' end='0x24000' /><slave name='adrv9371x_axi_os_adc_dma.s_axi' start='0x24000' end='0x28000' /><slave name='adrv9371x_axi_adc_dma.s_axi' start='0x28000' end='0x2C000' /><slave name='adrv9371x_xcvr_tx_lane_pll.reconfig_avmm0' start='0x34000' end='0x35000' /><slave name='adrv9371x_xcvr_pll_reconfig.mgmt_avalon_slave' start='0x35000' end='0x35800' /><slave name='adrv9371x_xcvr_tx_core.jesd204_tx_avs' start='0x35800' end='0x35C00' /><slave name='adrv9371x_xcvr_rx_os_core.jesd204_rx_avs' start='0x35C00' end='0x36000' /><slave name='adrv9371x_xcvr_rx_core.jesd204_rx_avs' start='0x36000' end='0x36400' /><slave name='adrv9371x_ad9371_gpio.s1' start='0x36400' end='0x36420' /></address-map>]]></parameter>
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<parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='adrv9371x_axi_os_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='adrv9371x_axi_jesd_xcvr.s_axi' start='0x10000' end='0x20000' /><slave name='adrv9371x_axi_dac_dma.s_axi' start='0x20000' end='0x24000' /><slave name='adrv9371x_axi_os_adc_dma.s_axi' start='0x24000' end='0x28000' /><slave name='adrv9371x_axi_adc_dma.s_axi' start='0x28000' end='0x2C000' /><slave name='adrv9371x_xcvr_tx_lane_pll.reconfig_avmm0' start='0x34000' end='0x35000' /><slave name='adrv9371x_xcvr_pll_reconfig.mgmt_avalon_slave' start='0x35000' end='0x35800' /><slave name='adrv9371x_xcvr_tx_core.jesd204_tx_avs' start='0x35800' end='0x35C00' /><slave name='adrv9371x_xcvr_rx_os_core.jesd204_rx_avs' start='0x35C00' end='0x36000' /><slave name='adrv9371x_xcvr_rx_core.jesd204_rx_avs' start='0x36000' end='0x36400' /><slave name='adrv9371x_ad9371_gpio.s1' start='0x36400' end='0x36420' /><slave name='adrv9371x_gpio_i.s1' start='0x36500' end='0x36510' /><slave name='adrv9371x_gpio_o.s1' start='0x36600' end='0x36620' /><slave name='adrv9371x_spi.spi_control_port' start='0x36700' end='0x36720' /></address-map>]]></parameter>
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<parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 18" />
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<parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_a10soc" />
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</module>
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@ -518,6 +545,24 @@
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<parameter name="baseAddress" value="0x00036400" />
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<parameter name="defaultConnection" value="false" />
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</connection>
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<connection
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kind="avalon"
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version="15.1"
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start="a10soc.sys_cpu_m_avl"
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end="adrv9371x.avl_gpio_i">
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<parameter name="arbitrationPriority" value="1" />
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<parameter name="baseAddress" value="0x00036500" />
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<parameter name="defaultConnection" value="false" />
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</connection>
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<connection
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kind="avalon"
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version="15.1"
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start="a10soc.sys_cpu_m_avl"
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end="adrv9371x.avl_gpio_o">
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<parameter name="arbitrationPriority" value="1" />
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<parameter name="baseAddress" value="0x00036600" />
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<parameter name="defaultConnection" value="false" />
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</connection>
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<connection
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kind="avalon"
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version="15.1"
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@ -536,6 +581,15 @@
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<parameter name="baseAddress" value="0x00035c00" />
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<parameter name="defaultConnection" value="false" />
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</connection>
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<connection
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kind="avalon"
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version="15.1"
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start="a10soc.sys_cpu_m_avl"
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end="adrv9371x.avl_spi">
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<parameter name="arbitrationPriority" value="1" />
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<parameter name="baseAddress" value="0x00036700" />
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<parameter name="defaultConnection" value="false" />
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</connection>
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<connection
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kind="avalon"
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version="15.1"
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@ -642,6 +696,13 @@
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end="adrv9371x.axi_dac_dma_intr">
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<parameter name="irqNumber" value="2" />
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</connection>
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<connection
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kind="interrupt"
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version="15.1"
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start="a10soc.hps_irq0"
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end="adrv9371x.spi_irq">
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<parameter name="irqNumber" value="4" />
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</connection>
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<connection
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kind="reset"
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version="15.1"
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@ -187,8 +187,6 @@ module system_top (
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.hps_ddr_mem_dbi_n (hps_ddr_dbi_n),
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.hps_ddr_oct_oct_rzqin (hps_ddr_rzq),
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.hps_ddr_ref_clk_clk (hps_ddr_ref_clk),
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.hps_gpio_gp_in (gpio_i),
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.hps_gpio_gp_out (gpio_o),
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.hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk),
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.hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]),
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.hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]),
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@ -233,15 +231,15 @@ module system_top (
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.hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]),
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.hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]),
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.hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]),
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.hps_spi0_mosi_o (spi_mosi),
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.hps_spi0_miso_i (spi_miso),
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.hps_spi0_mosi_o (),
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.hps_spi0_miso_i (),
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.hps_spi0_ss_in_n (1'b1),
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.hps_spi0_mosi_oe (),
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.hps_spi0_ss0_n_o (spi_csn_ad9528),
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.hps_spi0_ss1_n_o (spi_csn_ad9371),
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.hps_spi0_ss0_n_o (),
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.hps_spi0_ss1_n_o (),
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.hps_spi0_ss2_n_o (),
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.hps_spi0_ss3_n_o (),
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.hps_spi0_sclk_clk (spi_clk),
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.hps_spi0_sclk_clk (),
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.hps_spi1_mosi_o (),
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.hps_spi1_miso_i (1'b0),
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.hps_spi1_ss_in_n (1'b1),
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@ -252,17 +250,23 @@ module system_top (
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.hps_spi1_ss3_n_o (),
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.hps_spi1_sclk_clk (),
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.ref_clk_clk (ref_clk1),
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.rx_data_rx_serial_data (rx_data[1:0]),
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.rx_os_data_rx_serial_data (rx_data[3:2]),
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.rx_os_sync_rx_sync (rx_os_sync),
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.rx_os_sysref_rx_ext_sysref_in (sysref),
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.rx_sync_rx_sync (rx_sync),
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.rx_sysref_rx_ext_sysref_in (sysref),
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.sys_clk_clk (sys_clk),
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.sys_reset_reset_n (sys_resetn),
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.tx_data_tx_serial_data (tx_data),
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.tx_sync_tx_sync (tx_sync),
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.tx_sysref_tx_ext_sysref_in (sysref));
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.rx_data_rx_serial_data (rx_data[1:0]),
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.rx_os_data_rx_serial_data (rx_data[3:2]),
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.rx_os_sync_rx_sync (rx_os_sync),
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.rx_os_sysref_rx_ext_sysref_in (sysref),
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.rx_sync_rx_sync (rx_sync),
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.rx_sysref_rx_ext_sysref_in (sysref),
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.sys_clk_clk (sys_clk),
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.sys_reset_reset_n (sys_resetn),
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.tx_data_tx_serial_data (tx_data),
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.tx_sync_tx_sync (tx_sync),
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.tx_sysref_tx_ext_sysref_in (sysref),
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.gpio_i_export (gpio_i),
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.gpio_o_export (gpio_o),
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.spi_MISO (spi_miso),
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.spi_MOSI (spi_mosi),
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.spi_SCLK (spi_clk),
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.spi_SS_n ({spi_csn_ad9528, spi_csn_ad9371}));
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endmodule
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@ -181,6 +181,30 @@
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type = "boolean";
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}
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}
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element gpio_i
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{
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datum _sortIndex
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{
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value = "23";
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type = "int";
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}
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}
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element gpio_o
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{
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datum _sortIndex
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{
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value = "22";
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type = "int";
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}
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}
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element spi
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{
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datum _sortIndex
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{
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value = "24";
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type = "int";
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}
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}
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element sys_clk
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{
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datum _sortIndex
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@ -313,6 +337,8 @@
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internal="ad9371_gpio.s1"
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type="avalon"
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dir="end" />
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<interface name="avl_gpio_i" internal="gpio_i.s1" type="avalon" dir="end" />
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<interface name="avl_gpio_o" internal="gpio_o.s1" type="avalon" dir="end" />
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<interface
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name="avl_rx_jesd"
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internal="xcvr_rx_core.jesd204_rx_avs"
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@ -325,6 +351,11 @@
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dir="end" />
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<interface name="avl_rx_os_xcvr" internal="xcvr_rx_os_core.reconfig_avmm" />
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<interface name="avl_rx_xcvr" internal="xcvr_rx_core.reconfig_avmm" />
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<interface
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name="avl_spi"
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internal="spi.spi_control_port"
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type="avalon"
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dir="end" />
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<interface
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name="avl_tx_jesd"
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internal="xcvr_tx_core.jesd204_tx_avs"
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@ -404,6 +435,16 @@
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internal="axi_os_jesd_xcvr.s_axi"
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type="axi4lite"
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dir="end" />
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<interface
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name="gpio_i"
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internal="gpio_i.external_connection"
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type="conduit"
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dir="end" />
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<interface
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name="gpio_o"
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internal="gpio_o.external_connection"
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type="conduit"
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dir="end" />
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<interface
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name="rx_data"
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internal="xcvr_rx_core.rx_serial_data"
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@ -434,6 +475,8 @@
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internal="axi_jesd_xcvr.if_rx_ext_sysref_in"
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type="conduit"
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dir="end" />
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<interface name="spi" internal="spi.external" type="conduit" dir="end" />
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<interface name="spi_irq" internal="spi.irq" type="interrupt" dir="end" />
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<interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
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<interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
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<interface
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@ -558,6 +601,50 @@
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<parameter name="CHANNEL_DATA_WIDTH" value="32" />
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<parameter name="NUM_OF_CHANNELS" value="4" />
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</module>
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<module name="gpio_i" kind="altera_avalon_pio" version="15.1" enabled="1">
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<parameter name="bitClearingEdgeCapReg" value="false" />
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<parameter name="bitModifyingOutReg" value="false" />
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<parameter name="captureEdge" value="false" />
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<parameter name="clockRate" value="50000000" />
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<parameter name="direction" value="Input" />
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<parameter name="edgeType" value="RISING" />
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<parameter name="generateIRQ" value="false" />
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<parameter name="irqType" value="LEVEL" />
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<parameter name="resetValue" value="0" />
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<parameter name="simDoTestBenchWiring" value="false" />
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<parameter name="simDrivenValue" value="0" />
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<parameter name="width" value="32" />
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</module>
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<module name="gpio_o" kind="altera_avalon_pio" version="15.1" enabled="1">
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<parameter name="bitClearingEdgeCapReg" value="false" />
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<parameter name="bitModifyingOutReg" value="true" />
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<parameter name="captureEdge" value="false" />
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<parameter name="clockRate" value="50000000" />
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<parameter name="direction" value="Output" />
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<parameter name="edgeType" value="RISING" />
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<parameter name="generateIRQ" value="false" />
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<parameter name="irqType" value="LEVEL" />
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<parameter name="resetValue" value="0" />
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<parameter name="simDoTestBenchWiring" value="false" />
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<parameter name="simDrivenValue" value="0" />
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<parameter name="width" value="32" />
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</module>
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<module name="spi" kind="altera_avalon_spi" version="15.1" enabled="1">
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<parameter name="avalonSpec" value="2.0" />
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<parameter name="clockPhase" value="1" />
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<parameter name="clockPolarity" value="1" />
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<parameter name="dataWidth" value="8" />
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<parameter name="disableAvalonFlowControl" value="false" />
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<parameter name="inputClockRate" value="50000000" />
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<parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
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<parameter name="insertSync" value="false" />
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<parameter name="lsbOrderedFirst" value="false" />
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<parameter name="masterSPI" value="true" />
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<parameter name="numberOfSlaves" value="2" />
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<parameter name="syncRegDepth" value="2" />
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<parameter name="targetClockRate" value="5000000" />
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<parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
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</module>
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<module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
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<parameter name="DERIVED_CLOCK_RATE" value="0" />
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<parameter name="EXPLICIT_CLOCK_RATE" value="50000000" />
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@ -1240,6 +1327,9 @@
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version="15.1"
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start="sys_clk.out_clk"
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end="ad9371_gpio.clk" />
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<connection kind="clock" version="15.1" start="sys_clk.out_clk" end="gpio_o.clk" />
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<connection kind="clock" version="15.1" start="sys_clk.out_clk" end="gpio_i.clk" />
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<connection kind="clock" version="15.1" start="sys_clk.out_clk" end="spi.clk" />
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<connection
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kind="clock"
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version="15.1"
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@ -2134,6 +2224,17 @@
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version="15.1"
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||||
start="sys_rst.out_reset"
|
||||
end="ad9371_gpio.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="gpio_o.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="gpio_i.reset" />
|
||||
<connection kind="reset" version="15.1" start="sys_rst.out_reset" end="spi.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
|
|
|
|||
|
|
@ -311,9 +311,7 @@
|
|||
dir="end" />
|
||||
<interface
|
||||
name="hps_gpio"
|
||||
internal="arria10_hps_0.h2f_gp"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
internal="arria10_hps_0.h2f_gp" />
|
||||
<interface
|
||||
name="hps_io"
|
||||
internal="arria10_hps_0.hps_io"
|
||||
|
|
@ -470,7 +468,7 @@
|
|||
<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT" value="100" />
|
||||
<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT" value="100" />
|
||||
<parameter name="GPIO_REF_CLK" value="4" />
|
||||
<parameter name="GP_Enable" value="true" />
|
||||
<parameter name="GP_Enable" value="false" />
|
||||
<parameter name="H2F_AXI_CLOCK_FREQ" value="100" />
|
||||
<parameter name="H2F_COLD_RST_Enable" value="false" />
|
||||
<parameter name="H2F_CTI_CLOCK_FREQ" value="100" />
|
||||
|
|
@ -1556,7 +1554,7 @@
|
|||
<parameter name="PIPELINE_RESPONSE" value="1" />
|
||||
<parameter name="SYMBOL_WIDTH" value="8" />
|
||||
<parameter name="SYSINFO_ADDR_WIDTH" value="10" />
|
||||
<parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
|
||||
<parameter name="USE_AUTO_ADDRESS_WIDTH" value="1" />
|
||||
<parameter name="USE_RESPONSE" value="0" />
|
||||
</module>
|
||||
<module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
|
||||
|
|
|
|||
Loading…
Reference in New Issue