From 452d4706d3b95eb08c7b54d5431145c6204d3484 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 22 Jul 2016 17:50:18 +0300 Subject: [PATCH] kcu105: Update base project to 2015.4.2 - change part to revision 1.1 of the board --- projects/common/kcu105/kcu105_system_bd.tcl | 46 ++---- .../common/kcu105/kcu105_system_constr.xdc | 132 ------------------ projects/scripts/adi_project.tcl | 2 +- 3 files changed, 15 insertions(+), 165 deletions(-) diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl index 3bbc41c3f..82791a84f 100644 --- a/projects/common/kcu105/kcu105_system_bd.tcl +++ b/projects/common/kcu105/kcu105_system_bd.tcl @@ -80,32 +80,24 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s # instance: ddr (mig) -set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:1.1 axi_ddr_cntrl] -source $ad_hdl_dir/projects/common/kcu105/kcu105_system_mig.tcl +set axi_ddr_cntrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:1.1 axi_ddr_cntrl ] +set_property -dict [list CONFIG.C0_CLOCK_BOARD_INTERFACE {default_sysclk_300}] $axi_ddr_cntrl +set_property -dict [list CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram}] $axi_ddr_cntrl +set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset}] $axi_ddr_cntrl +set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] $axi_ddr_cntrl +set_property -dict [list CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {200}] $axi_ddr_cntrl set axi_ddr_cntrl_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_ddr_cntrl_rstgen] # instance: default peripherals -set axi_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 axi_ethernet_clkgen] -set_property -dict [list CONFIG.PRIM_IN_FREQ {625}] $axi_ethernet_clkgen -set_property -dict [list CONFIG.PRIM_SOURCE {Differential_clock_capable_pin}] $axi_ethernet_clkgen -set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125}] $axi_ethernet_clkgen -set_property -dict [list CONFIG.CLKOUT2_USED {true}] $axi_ethernet_clkgen -set_property -dict [list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {312}] $axi_ethernet_clkgen -set_property -dict [list CONFIG.CLKOUT3_USED {true}] $axi_ethernet_clkgen -set_property -dict [list CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {625}] $axi_ethernet_clkgen -set_property -dict [list CONFIG.CLKOUT4_USED {false}] $axi_ethernet_clkgen -set_property -dict [list CONFIG.USE_LOCKED {true}] $axi_ethernet_clkgen -set_property -dict [list CONFIG.USE_RESET {false}] $axi_ethernet_clkgen - -set axi_ethernet_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_ethernet_rstgen] -set axi_ethernet_idelayctrl [create_bd_cell -type ip -vlnv xilinx.com:ip:util_idelay_ctrl:1.0 axi_ethernet_idelayctrl] - set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:7.0 axi_ethernet] -set_property -dict [list CONFIG.PHY_TYPE {SGMII}] $axi_ethernet -set_property -dict [list CONFIG.ENABLE_LVDS {true}] $axi_ethernet -set_property -dict [list CONFIG.SupportLevel {0}] $axi_ethernet +set_property -dict [list CONFIG.SupportLevel {1}] $axi_ethernet +set_property -dict [list CONFIG.ETHERNET_BOARD_INTERFACE {sgmii_lvds}] $axi_ethernet +set_property -dict [list CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc}] $axi_ethernet +set_property -dict [list CONFIG.PHYRST_BOARD_INTERFACE {phy_reset_out}] $axi_ethernet +set_property -dict [list CONFIG.DIFFCLK_BOARD_INTERFACE {sgmii_phyclk}] $axi_ethernet +set_property -dict [list CONFIG.lvdsclkrate {625}] $axi_ethernet set_property -dict [list CONFIG.TXCSUM {Full}] $axi_ethernet set_property -dict [list CONFIG.RXCSUM {Full}] $axi_ethernet set_property -dict [list CONFIG.TXMEM {8k}] $axi_ethernet @@ -210,13 +202,12 @@ ad_connect c0_ddr4 axi_ddr_cntrl/C0_DDR4 ad_connect sys_clk axi_ddr_cntrl/C0_SYS_CLK ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_rstgen/ext_reset_in -ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst axi_ethernet_rstgen/ext_reset_in ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst axi_ddr_cntrl_rstgen/ext_reset_in ad_connect sys_mem_clk axi_ddr_cntrl_rstgen/slowest_sync_clk # defaults (ethernet) -ad_connect phy_clk axi_ethernet_clkgen/CLK_IN1_D +ad_connect phy_clk axi_ethernet/lvds_clk ad_connect mdio axi_ethernet/mdio ad_connect sgmii axi_ethernet/sgmii ad_connect axi_ethernet/s_axis_txd axi_ethernet_dma/M_AXIS_MM2S @@ -224,20 +215,11 @@ ad_connect axi_ethernet/s_axis_txc axi_ethernet_dma/M_AXIS_CNTRL ad_connect axi_ethernet/m_axis_rxd axi_ethernet_dma/S_AXIS_S2MM ad_connect axi_ethernet/m_axis_rxs axi_ethernet_dma/S_AXIS_STS ad_connect phy_sd axi_ethernet/signal_detect -ad_connect sys_cpu_resetn phy_rst_n -ad_connect axi_ethernet_clkgen/clk_out1 axi_ethernet/clk125m -ad_connect axi_ethernet_clkgen/clk_out1 axi_ethernet_rstgen/slowest_sync_clk -ad_connect axi_ethernet_clkgen/clk_out2 axi_ethernet/clk312 -ad_connect axi_ethernet_clkgen/clk_out3 axi_ethernet/clk625 -ad_connect axi_ethernet_clkgen/locked axi_ethernet/mmcm_locked -ad_connect axi_ethernet_rstgen/peripheral_reset axi_ethernet/rst_125 +ad_connect phy_rst_n axi_ethernet/phy_rst_n ad_connect axi_ethernet/axi_txd_arstn axi_ethernet_dma/mm2s_prmry_reset_out_n ad_connect axi_ethernet/axi_txc_arstn axi_ethernet_dma/mm2s_cntrl_reset_out_n ad_connect axi_ethernet/axi_rxd_arstn axi_ethernet_dma/s2mm_prmry_reset_out_n ad_connect axi_ethernet/axi_rxs_arstn axi_ethernet_dma/s2mm_sts_reset_out_n -ad_connect axi_ethernet_idelayctrl/rdy axi_ethernet/idelay_rdy_in -ad_connect axi_ethernet_idelayctrl/rst axi_ethernet_rstgen/peripheral_reset -ad_connect axi_ethernet_idelayctrl/ref_clk axi_ethernet_clkgen/clk_out3 # defaults (misc) diff --git a/projects/common/kcu105/kcu105_system_constr.xdc b/projects/common/kcu105/kcu105_system_constr.xdc index fb6306582..353122bca 100644 --- a/projects/common/kcu105/kcu105_system_constr.xdc +++ b/projects/common/kcu105/kcu105_system_constr.xdc @@ -3,21 +3,6 @@ set_property -dict {PACKAGE_PIN AN8 IOSTANDARD LVCMOS18} [get_ports sys_rst] -# clocks - -set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVDS_25} [get_ports phy_clk_p] -set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVDS_25} [get_ports phy_clk_n] - -# ethernet - -set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS18} [get_ports mdio_mdc] -set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVCMOS18} [get_ports mdio_mdio] -set_property -dict {PACKAGE_PIN J23 IOSTANDARD LVCMOS18} [get_ports phy_rst_n] -set_property -dict {PACKAGE_PIN N24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_tx_p] -set_property -dict {PACKAGE_PIN M24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_tx_n] -set_property -dict {PACKAGE_PIN P24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_rx_p] -set_property -dict {PACKAGE_PIN P25 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_rx_n] - # uart set_property -dict {PACKAGE_PIN K26 IOSTANDARD LVCMOS18} [get_ports uart_sout] @@ -56,125 +41,8 @@ set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18} [get_ports iic_sda set_property -dict {PACKAGE_PIN AK17} [get_ports sys_clk_p] set_property -dict {PACKAGE_PIN AK16} [get_ports sys_clk_n] -set_property -dict {PACKAGE_PIN AH14} [get_ports ddr4_act_n] -set_property -dict {PACKAGE_PIN AE17} [get_ports ddr4_addr[0]] -set_property -dict {PACKAGE_PIN AH17} [get_ports ddr4_addr[1]] -set_property -dict {PACKAGE_PIN AE18} [get_ports ddr4_addr[2]] -set_property -dict {PACKAGE_PIN AJ15} [get_ports ddr4_addr[3]] -set_property -dict {PACKAGE_PIN AG16} [get_ports ddr4_addr[4]] -set_property -dict {PACKAGE_PIN AL17} [get_ports ddr4_addr[5]] -set_property -dict {PACKAGE_PIN AK18} [get_ports ddr4_addr[6]] -set_property -dict {PACKAGE_PIN AG17} [get_ports ddr4_addr[7]] -set_property -dict {PACKAGE_PIN AF18} [get_ports ddr4_addr[8]] -set_property -dict {PACKAGE_PIN AH19} [get_ports ddr4_addr[9]] -set_property -dict {PACKAGE_PIN AF15} [get_ports ddr4_addr[10]] -set_property -dict {PACKAGE_PIN AD19} [get_ports ddr4_addr[11]] -set_property -dict {PACKAGE_PIN AJ14} [get_ports ddr4_addr[12]] -set_property -dict {PACKAGE_PIN AG19} [get_ports ddr4_addr[13]] -set_property -dict {PACKAGE_PIN AD16} [get_ports ddr4_addr[14]] -set_property -dict {PACKAGE_PIN AG14} [get_ports ddr4_addr[15]] -set_property -dict {PACKAGE_PIN AF14} [get_ports ddr4_addr[16]] -set_property -dict {PACKAGE_PIN AF17} [get_ports ddr4_ba[0]] -set_property -dict {PACKAGE_PIN AL15} [get_ports ddr4_ba[1]] -set_property -dict {PACKAGE_PIN AG15} [get_ports ddr4_bg[0]] -set_property -dict {PACKAGE_PIN AE16} [get_ports ddr4_ck_p] -set_property -dict {PACKAGE_PIN AE15} [get_ports ddr4_ck_n] -set_property -dict {PACKAGE_PIN AD15} [get_ports ddr4_cke[0]] -set_property -dict {PACKAGE_PIN AL19} [get_ports ddr4_cs_n[0]] -set_property -dict {PACKAGE_PIN AD21} [get_ports ddr4_dm_n[0]] -set_property -dict {PACKAGE_PIN AE25} [get_ports ddr4_dm_n[1]] -set_property -dict {PACKAGE_PIN AJ21} [get_ports ddr4_dm_n[2]] -set_property -dict {PACKAGE_PIN AM21} [get_ports ddr4_dm_n[3]] -set_property -dict {PACKAGE_PIN AH26} [get_ports ddr4_dm_n[4]] -set_property -dict {PACKAGE_PIN AN26} [get_ports ddr4_dm_n[5]] -set_property -dict {PACKAGE_PIN AJ29} [get_ports ddr4_dm_n[6]] -set_property -dict {PACKAGE_PIN AL32} [get_ports ddr4_dm_n[7]] -set_property -dict {PACKAGE_PIN AE23} [get_ports ddr4_dq[0]] -set_property -dict {PACKAGE_PIN AG20} [get_ports ddr4_dq[1]] -set_property -dict {PACKAGE_PIN AF22} [get_ports ddr4_dq[2]] -set_property -dict {PACKAGE_PIN AF20} [get_ports ddr4_dq[3]] -set_property -dict {PACKAGE_PIN AE22} [get_ports ddr4_dq[4]] -set_property -dict {PACKAGE_PIN AD20} [get_ports ddr4_dq[5]] -set_property -dict {PACKAGE_PIN AG22} [get_ports ddr4_dq[6]] -set_property -dict {PACKAGE_PIN AE20} [get_ports ddr4_dq[7]] -set_property -dict {PACKAGE_PIN AJ24} [get_ports ddr4_dq[8]] -set_property -dict {PACKAGE_PIN AG24} [get_ports ddr4_dq[9]] -set_property -dict {PACKAGE_PIN AJ23} [get_ports ddr4_dq[10]] -set_property -dict {PACKAGE_PIN AF23} [get_ports ddr4_dq[11]] -set_property -dict {PACKAGE_PIN AH23} [get_ports ddr4_dq[12]] -set_property -dict {PACKAGE_PIN AF24} [get_ports ddr4_dq[13]] -set_property -dict {PACKAGE_PIN AH22} [get_ports ddr4_dq[14]] -set_property -dict {PACKAGE_PIN AG25} [get_ports ddr4_dq[15]] -set_property -dict {PACKAGE_PIN AL22} [get_ports ddr4_dq[16]] -set_property -dict {PACKAGE_PIN AL25} [get_ports ddr4_dq[17]] -set_property -dict {PACKAGE_PIN AM20} [get_ports ddr4_dq[18]] -set_property -dict {PACKAGE_PIN AK23} [get_ports ddr4_dq[19]] -set_property -dict {PACKAGE_PIN AK22} [get_ports ddr4_dq[20]] -set_property -dict {PACKAGE_PIN AL24} [get_ports ddr4_dq[21]] -set_property -dict {PACKAGE_PIN AL20} [get_ports ddr4_dq[22]] -set_property -dict {PACKAGE_PIN AL23} [get_ports ddr4_dq[23]] -set_property -dict {PACKAGE_PIN AM24} [get_ports ddr4_dq[24]] -set_property -dict {PACKAGE_PIN AN23} [get_ports ddr4_dq[25]] -set_property -dict {PACKAGE_PIN AN24} [get_ports ddr4_dq[26]] -set_property -dict {PACKAGE_PIN AP23} [get_ports ddr4_dq[27]] -set_property -dict {PACKAGE_PIN AP25} [get_ports ddr4_dq[28]] -set_property -dict {PACKAGE_PIN AN22} [get_ports ddr4_dq[29]] -set_property -dict {PACKAGE_PIN AP24} [get_ports ddr4_dq[30]] -set_property -dict {PACKAGE_PIN AM22} [get_ports ddr4_dq[31]] -set_property -dict {PACKAGE_PIN AH28} [get_ports ddr4_dq[32]] -set_property -dict {PACKAGE_PIN AK26} [get_ports ddr4_dq[33]] -set_property -dict {PACKAGE_PIN AK28} [get_ports ddr4_dq[34]] -set_property -dict {PACKAGE_PIN AM27} [get_ports ddr4_dq[35]] -set_property -dict {PACKAGE_PIN AJ28} [get_ports ddr4_dq[36]] -set_property -dict {PACKAGE_PIN AH27} [get_ports ddr4_dq[37]] -set_property -dict {PACKAGE_PIN AK27} [get_ports ddr4_dq[38]] -set_property -dict {PACKAGE_PIN AM26} [get_ports ddr4_dq[39]] -set_property -dict {PACKAGE_PIN AL30} [get_ports ddr4_dq[40]] -set_property -dict {PACKAGE_PIN AP29} [get_ports ddr4_dq[41]] -set_property -dict {PACKAGE_PIN AM30} [get_ports ddr4_dq[42]] -set_property -dict {PACKAGE_PIN AN28} [get_ports ddr4_dq[43]] -set_property -dict {PACKAGE_PIN AL29} [get_ports ddr4_dq[44]] -set_property -dict {PACKAGE_PIN AP28} [get_ports ddr4_dq[45]] -set_property -dict {PACKAGE_PIN AM29} [get_ports ddr4_dq[46]] -set_property -dict {PACKAGE_PIN AN27} [get_ports ddr4_dq[47]] -set_property -dict {PACKAGE_PIN AH31} [get_ports ddr4_dq[48]] -set_property -dict {PACKAGE_PIN AH32} [get_ports ddr4_dq[49]] -set_property -dict {PACKAGE_PIN AJ34} [get_ports ddr4_dq[50]] -set_property -dict {PACKAGE_PIN AK31} [get_ports ddr4_dq[51]] -set_property -dict {PACKAGE_PIN AJ31} [get_ports ddr4_dq[52]] -set_property -dict {PACKAGE_PIN AJ30} [get_ports ddr4_dq[53]] -set_property -dict {PACKAGE_PIN AH34} [get_ports ddr4_dq[54]] -set_property -dict {PACKAGE_PIN AK32} [get_ports ddr4_dq[55]] -set_property -dict {PACKAGE_PIN AN33} [get_ports ddr4_dq[56]] -set_property -dict {PACKAGE_PIN AP33} [get_ports ddr4_dq[57]] -set_property -dict {PACKAGE_PIN AM34} [get_ports ddr4_dq[58]] -set_property -dict {PACKAGE_PIN AP31} [get_ports ddr4_dq[59]] -set_property -dict {PACKAGE_PIN AM32} [get_ports ddr4_dq[60]] -set_property -dict {PACKAGE_PIN AN31} [get_ports ddr4_dq[61]] -set_property -dict {PACKAGE_PIN AL34} [get_ports ddr4_dq[62]] -set_property -dict {PACKAGE_PIN AN32} [get_ports ddr4_dq[63]] -set_property -dict {PACKAGE_PIN AG21} [get_ports ddr4_dqs_p[0]] -set_property -dict {PACKAGE_PIN AH24} [get_ports ddr4_dqs_p[1]] -set_property -dict {PACKAGE_PIN AJ20} [get_ports ddr4_dqs_p[2]] -set_property -dict {PACKAGE_PIN AP20} [get_ports ddr4_dqs_p[3]] -set_property -dict {PACKAGE_PIN AL27} [get_ports ddr4_dqs_p[4]] -set_property -dict {PACKAGE_PIN AN29} [get_ports ddr4_dqs_p[5]] -set_property -dict {PACKAGE_PIN AH33} [get_ports ddr4_dqs_p[6]] -set_property -dict {PACKAGE_PIN AN34} [get_ports ddr4_dqs_p[7]] -set_property -dict {PACKAGE_PIN AH21} [get_ports ddr4_dqs_n[0]] -set_property -dict {PACKAGE_PIN AJ25} [get_ports ddr4_dqs_n[1]] -set_property -dict {PACKAGE_PIN AK20} [get_ports ddr4_dqs_n[2]] -set_property -dict {PACKAGE_PIN AP21} [get_ports ddr4_dqs_n[3]] -set_property -dict {PACKAGE_PIN AL28} [get_ports ddr4_dqs_n[4]] -set_property -dict {PACKAGE_PIN AP30} [get_ports ddr4_dqs_n[5]] -set_property -dict {PACKAGE_PIN AJ33} [get_ports ddr4_dqs_n[6]] -set_property -dict {PACKAGE_PIN AP34} [get_ports ddr4_dqs_n[7]] -set_property -dict {PACKAGE_PIN AJ18} [get_ports ddr4_odt[0]] -set_property -dict {PACKAGE_PIN AL18} [get_ports ddr4_reset_n] set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 44] set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 45] set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 46] -set_false_path -to [get_pins -hier -filter {name =~ *axi_ethernet_idelayctrl*/RST}] - diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl index 77101fc33..cce18d679 100644 --- a/projects/scripts/adi_project.tcl +++ b/projects/scripts/adi_project.tcl @@ -47,7 +47,7 @@ proc adi_project_create {project_name {mode 0}} { } if [regexp "_kcu105$" $project_name] { set p_device "xcku040-ffva1156-2-e" - set p_board "xilinx.com:kcu105:part0:1.0" + set p_board "xilinx.com:kcu105:part0:1.1" set sys_zynq 0 } if [regexp "_zed$" $project_name] {