From 43a06950aa4d29ea6b3301ad574cb2e93fc5bad7 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Thu, 29 Jun 2017 15:03:54 +0300 Subject: [PATCH] axi_ad9361: Altera fix lvds interface - use internal serdes pll --- .../altera/axi_ad9361_alt_lvds_rx.v | 202 +++++++ .../altera/axi_ad9361_alt_lvds_tx.v | 186 ++++++ .../axi_ad9361/altera/axi_ad9361_lvds_if.v | 557 +++++------------- library/axi_ad9361/axi_ad9361_hw.tcl | 12 +- 4 files changed, 538 insertions(+), 419 deletions(-) create mode 100644 library/axi_ad9361/altera/axi_ad9361_alt_lvds_rx.v create mode 100644 library/axi_ad9361/altera/axi_ad9361_alt_lvds_tx.v diff --git a/library/axi_ad9361/altera/axi_ad9361_alt_lvds_rx.v b/library/axi_ad9361/altera/axi_ad9361_alt_lvds_rx.v new file mode 100644 index 000000000..9f48dd55a --- /dev/null +++ b/library/axi_ad9361/altera/axi_ad9361_alt_lvds_rx.v @@ -0,0 +1,202 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9361_alt_lvds_rx ( + + // physical interface (receive) + + rx_clk_in_p, + rx_clk_in_n, + rx_frame_in_p, + rx_frame_in_n, + rx_data_in_p, + rx_data_in_n, + + // data interface + + clk, + rx_frame, + rx_data_0, + rx_data_1, + rx_data_2, + rx_data_3, + rx_locked); + + // physical interface (receive) + + input rx_clk_in_p; + input rx_clk_in_n; + input rx_frame_in_p; + input rx_frame_in_n; + input [ 5:0] rx_data_in_p; + input [ 5:0] rx_data_in_n; + + // data interface + + output clk; + output [ 3:0] rx_frame; + output [ 5:0] rx_data_0; + output [ 5:0] rx_data_1; + output [ 5:0] rx_data_2; + output [ 5:0] rx_data_3; + output rx_locked; + + // internal signals + + wire [27:0] rx_data_s; + + // instantiations + + assign rx_frame[3] = rx_data_s[24]; + assign rx_frame[2] = rx_data_s[25]; + assign rx_frame[1] = rx_data_s[26]; + assign rx_frame[0] = rx_data_s[27]; + assign rx_data_3[5] = rx_data_s[20]; + assign rx_data_3[4] = rx_data_s[16]; + assign rx_data_3[3] = rx_data_s[12]; + assign rx_data_3[2] = rx_data_s[ 8]; + assign rx_data_3[1] = rx_data_s[ 4]; + assign rx_data_3[0] = rx_data_s[ 0]; + assign rx_data_2[5] = rx_data_s[21]; + assign rx_data_2[4] = rx_data_s[17]; + assign rx_data_2[3] = rx_data_s[13]; + assign rx_data_2[2] = rx_data_s[ 9]; + assign rx_data_2[1] = rx_data_s[ 5]; + assign rx_data_2[0] = rx_data_s[ 1]; + assign rx_data_1[5] = rx_data_s[22]; + assign rx_data_1[4] = rx_data_s[18]; + assign rx_data_1[3] = rx_data_s[14]; + assign rx_data_1[2] = rx_data_s[10]; + assign rx_data_1[1] = rx_data_s[ 6]; + assign rx_data_1[0] = rx_data_s[ 2]; + assign rx_data_0[5] = rx_data_s[23]; + assign rx_data_0[4] = rx_data_s[19]; + assign rx_data_0[3] = rx_data_s[15]; + assign rx_data_0[2] = rx_data_s[11]; + assign rx_data_0[1] = rx_data_s[ 7]; + assign rx_data_0[0] = rx_data_s[ 3]; + + altlvds_rx #( + .buffer_implementation ("RAM"), + .cds_mode ("UNUSED"), + .common_rx_tx_pll ("ON"), + .data_align_rollover (4), + .data_rate ("500.0 Mbps"), + .deserialization_factor (4), + .dpa_initial_phase_value (0), + .dpll_lock_count (0), + .dpll_lock_window (0), + .enable_clock_pin_mode ("UNUSED"), + .enable_dpa_align_to_rising_edge_only ("OFF"), + .enable_dpa_calibration ("ON"), + .enable_dpa_fifo ("UNUSED"), + .enable_dpa_initial_phase_selection ("OFF"), + .enable_dpa_mode ("OFF"), + .enable_dpa_pll_calibration ("OFF"), + .enable_soft_cdr_mode ("OFF"), + .implement_in_les ("OFF"), + .inclock_boost (0), + .inclock_data_alignment ("EDGE_ALIGNED"), + .inclock_period (4000), + .inclock_phase_shift (0), + .input_data_rate (500), + .intended_device_family ("Cyclone V"), + .lose_lock_on_one_change ("UNUSED"), + .lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_alt_lvds_rx"), + .lpm_type ("altlvds_rx"), + .number_of_channels (7), + .outclock_resource ("Regional clock"), + .pll_operation_mode ("NORMAL"), + .pll_self_reset_on_loss_lock ("UNUSED"), + .port_rx_channel_data_align ("PORT_UNUSED"), + .port_rx_data_align ("PORT_UNUSED"), + .refclk_frequency ("250.000000 MHz"), + .registered_data_align_input ("UNUSED"), + .registered_output ("ON"), + .reset_fifo_at_first_lock ("UNUSED"), + .rx_align_data_reg ("RISING_EDGE"), + .sim_dpa_is_negative_ppm_drift ("OFF"), + .sim_dpa_net_ppm_variation (0), + .sim_dpa_output_clock_phase_shift (0), + .use_coreclock_input ("OFF"), + .use_dpll_rawperror ("OFF"), + .use_external_pll ("OFF"), + .use_no_phase_shift ("ON"), + .x_on_bitslip ("ON"), + .clk_src_is_pll ("off")) + i_altlvds_rx ( + .rx_inclock (rx_clk_in_p), + .rx_in ({rx_frame_in_p, rx_data_in_p}), + .rx_outclock (clk), + .rx_out (rx_data_s), + .rx_locked (rx_locked), + .dpa_pll_cal_busy (), + .dpa_pll_recal (1'b0), + .pll_areset (1'b0), + .pll_phasecounterselect (), + .pll_phasedone (1'b1), + .pll_phasestep (), + .pll_phaseupdown (), + .pll_scanclk (), + .rx_cda_max (), + .rx_cda_reset ({7{1'b0}}), + .rx_channel_data_align ({7{1'b0}}), + .rx_coreclk ({7{1'b1}}), + .rx_data_align (1'b0), + .rx_data_align_reset (1'b0), + .rx_data_reset (1'b0), + .rx_deskew (1'b0), + .rx_divfwdclk (), + .rx_dpa_lock_reset ({7{1'b0}}), + .rx_dpa_locked (), + .rx_dpaclock (1'b0), + .rx_dpll_enable ({7{1'b1}}), + .rx_dpll_hold ({7{1'b0}}), + .rx_dpll_reset ({7{1'b0}}), + .rx_enable (1'b1), + .rx_fifo_reset ({7{1'b0}}), + .rx_pll_enable (1'b1), + .rx_readclock (1'b0), + .rx_reset ({7{1'b0}}), + .rx_syncclock (1'b0)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9361/altera/axi_ad9361_alt_lvds_tx.v b/library/axi_ad9361/altera/axi_ad9361_alt_lvds_tx.v new file mode 100644 index 000000000..2b96fccb6 --- /dev/null +++ b/library/axi_ad9361/altera/axi_ad9361_alt_lvds_tx.v @@ -0,0 +1,186 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9361_alt_lvds_tx ( + + // physical interface (transmit) + + tx_clk_out_p, + tx_clk_out_n, + tx_frame_out_p, + tx_frame_out_n, + tx_data_out_p, + tx_data_out_n, + + // data interface + + tx_clk, + clk, + tx_frame, + tx_data_0, + tx_data_1, + tx_data_2, + tx_data_3, + tx_locked); + + // physical interface (transmit) + + output tx_clk_out_p; + output tx_clk_out_n; + output tx_frame_out_p; + output tx_frame_out_n; + output [ 5:0] tx_data_out_p; + output [ 5:0] tx_data_out_n; + + // data interface + + input tx_clk; + input clk; + input [ 3:0] tx_frame; + input [ 5:0] tx_data_0; + input [ 5:0] tx_data_1; + input [ 5:0] tx_data_2; + input [ 5:0] tx_data_3; + output tx_locked; + + // internal registers + + reg [27:0] tx_data_n = 'd0; + reg [27:0] tx_data_p = 'd0; + + // internal signals + + wire core_clk; + wire [27:0] tx_data_s; + + // instantiations + + assign tx_clk_out_n = 1'd0; + assign tx_frame_out_n = 1'd0; + assign tx_data_out_n = 6'd0; + + assign tx_data_s[24] = tx_frame[3]; + assign tx_data_s[25] = tx_frame[2]; + assign tx_data_s[26] = tx_frame[1]; + assign tx_data_s[27] = tx_frame[0]; + assign tx_data_s[20] = tx_data_3[5]; + assign tx_data_s[16] = tx_data_3[4]; + assign tx_data_s[12] = tx_data_3[3]; + assign tx_data_s[ 8] = tx_data_3[2]; + assign tx_data_s[ 4] = tx_data_3[1]; + assign tx_data_s[ 0] = tx_data_3[0]; + assign tx_data_s[21] = tx_data_2[5]; + assign tx_data_s[17] = tx_data_2[4]; + assign tx_data_s[13] = tx_data_2[3]; + assign tx_data_s[ 9] = tx_data_2[2]; + assign tx_data_s[ 5] = tx_data_2[1]; + assign tx_data_s[ 1] = tx_data_2[0]; + assign tx_data_s[22] = tx_data_1[5]; + assign tx_data_s[18] = tx_data_1[4]; + assign tx_data_s[14] = tx_data_1[3]; + assign tx_data_s[10] = tx_data_1[2]; + assign tx_data_s[ 6] = tx_data_1[1]; + assign tx_data_s[ 2] = tx_data_1[0]; + assign tx_data_s[23] = tx_data_0[5]; + assign tx_data_s[19] = tx_data_0[4]; + assign tx_data_s[15] = tx_data_0[3]; + assign tx_data_s[11] = tx_data_0[2]; + assign tx_data_s[ 7] = tx_data_0[1]; + assign tx_data_s[ 3] = tx_data_0[0]; + + always @(negedge clk) begin + tx_data_n <= tx_data_s; + end + + always @(posedge core_clk) begin + tx_data_p <= tx_data_n; + end + + altlvds_tx #( + .center_align_msb ("UNUSED"), + .common_rx_tx_pll ("ON"), + .coreclock_divide_by (1), + .data_rate ("500.0 Mbps"), + .deserialization_factor (4), + .differential_drive (0), + .enable_clock_pin_mode ("UNUSED"), + .implement_in_les ("OFF"), + .inclock_boost (0), + .inclock_data_alignment ("EDGE_ALIGNED"), + .inclock_period (4000), + .inclock_phase_shift (0), + .intended_device_family ("Cyclone V"), + .lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_alt_lvds_tx"), + .lpm_type ("altlvds_tx"), + .multi_clock ("OFF"), + .number_of_channels (7), + .outclock_alignment ("EDGE_ALIGNED"), + .outclock_divide_by (2), + .outclock_duty_cycle (50), + .outclock_multiply_by (1), + .outclock_phase_shift (0), + .outclock_resource ("Regional clock"), + .output_data_rate (500), + .pll_compensation_mode ("AUTO"), + .pll_self_reset_on_loss_lock ("OFF"), + .preemphasis_setting (0), + .refclk_frequency ("250.000000 MHz"), + .registered_input ("TX_CORECLK"), + .use_external_pll ("OFF"), + .use_no_phase_shift ("ON"), + .vod_setting (0), + .clk_src_is_pll ("off")) + i_altlvds_tx ( + .tx_inclock (tx_clk), + .tx_coreclock (core_clk), + .tx_in (tx_data_p), + .tx_outclock (tx_clk_out_p), + .tx_out ({tx_frame_out_p, tx_data_out_p}), + .tx_locked (tx_locked), + .pll_areset (1'b0), + .sync_inclock (1'b0), + .tx_data_reset (1'b0), + .tx_enable (1'b1), + .tx_pll_enable (1'b1), + .tx_syncclock (1'b0)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9361/altera/axi_ad9361_lvds_if.v b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v index f9ebfbcba..67461e8db 100644 --- a/library/axi_ad9361/altera/axi_ad9361_lvds_if.v +++ b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v @@ -1,37 +1,35 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. // -// All rights reserved. +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. // -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. // -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. // -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -123,434 +121,167 @@ module axi_ad9361_lvds_if #( // internal registers reg [ 3:0] rx_frame = 'd0; - reg rx_error = 'd0; - reg rx_valid = 'd0; reg [ 5:0] rx_data_3 = 'd0; reg [ 5:0] rx_data_2 = 'd0; reg [ 5:0] rx_data_1 = 'd0; reg [ 5:0] rx_data_0 = 'd0; - reg [23:0] rx_data = 'd0; + reg rx_error_r2 = 'd0; + reg rx_valid_r2 = 'd0; + reg [23:0] rx_data_r2 = 'd0; + reg tx_data_sel = 'd0; + reg [47:0] tx_data = 'd0; reg [ 3:0] tx_frame = 'd0; - reg [ 3:0] tx_p_frame = 'd0; - reg [ 3:0] tx_n_frame = 'd0; - reg [ 5:0] tx_data_d_0 = 'd0; - reg [ 5:0] tx_data_d_1 = 'd0; - reg [ 5:0] tx_data_d_2 = 'd0; - reg [ 5:0] tx_data_d_3 = 'd0; - reg tx_data_sel = 'd0; - reg up_enable_int = 'd0; - reg up_txnrx_int = 'd0; - reg enable_up_m1 = 'd0; - reg txnrx_up_m1 = 'd0; - reg enable_up = 'd0; - reg txnrx_up = 'd0; - reg enable_int = 'd0; - reg txnrx_int = 'd0; - reg enable_n_int = 'd0; - reg txnrx_n_int = 'd0; - reg enable_p_int = 'd0; - reg txnrx_p_int = 'd0; - reg [ 5:0] tx_p_data_d_0 = 'd0; - reg [ 5:0] tx_p_data_d_1 = 'd0; - reg [ 5:0] tx_p_data_d_2 = 'd0; - reg [ 5:0] tx_p_data_d_3 = 'd0; - reg [ 5:0] tx_n_data_d_0 = 'd0; - reg [ 5:0] tx_n_data_d_1 = 'd0; - reg [ 5:0] tx_n_data_d_2 = 'd0; - reg [ 5:0] tx_n_data_d_3 = 'd0; - reg adc_n_valid = 'd0; - reg adc_p_valid = 'd0; - reg adc_n_status = 'd0; - reg adc_p_status = 'd0; - reg [47:0] adc_n_data = 'd0; - reg [47:0] adc_p_data = 'd0; + reg [ 5:0] tx_data_0 = 'd0; + reg [ 5:0] tx_data_1 = 'd0; + reg [ 5:0] tx_data_2 = 'd0; + reg [ 5:0] tx_data_3 = 'd0; // internal signals - wire s_clk; - wire loaden; - wire [ 7:0] phase_s; - wire [ 3:0] rx_frame_s; - wire [ 5:0] rx_data_s_3; - wire [ 5:0] rx_data_s_2; - wire [ 5:0] rx_data_s_1; - wire [ 5:0] rx_data_s_0; wire [ 3:0] rx_frame_inv_s; + wire tx_locked_s; + wire [ 3:0] rx_frame_s; + wire [ 5:0] rx_data_0_s; + wire [ 5:0] rx_data_1_s; + wire [ 5:0] rx_data_2_s; + wire [ 5:0] rx_data_3_s; + wire rx_locked_s; - // unused interface signals + // tdd support- - assign up_adc_drdata = 35'b0; - assign up_dac_drdata = 50'b0; - assign delay_locked = 1'b1; + assign enable = up_enable; + assign txnrx = up_txnrx; + + // defaults + + assign delay_locked = 1'd1; + + // receive data path interface assign rx_frame_inv_s = ~rx_frame; always @(posedge l_clk) begin rx_frame <= rx_frame_s; - rx_data_3 <= rx_data_s_3; - rx_data_2 <= rx_data_s_2; - rx_data_1 <= rx_data_s_1; - rx_data_0 <= rx_data_s_0; + rx_data_3 <= rx_data_3_s; + rx_data_2 <= rx_data_2_s; + rx_data_1 <= rx_data_1_s; + rx_data_0 <= rx_data_0_s; if (rx_frame_inv_s == rx_frame_s) begin - rx_error <= 1'b0; + rx_error_r2 <= 1'b0; end else begin - rx_error <= 1'b1; + rx_error_r2 <= 1'b1; end - case ({adc_r1_mode, rx_frame}) - // R2 Mode - 5'b01111: begin - rx_valid <= 1'b1; - rx_data[23:12] <= {rx_data_1, rx_data_3}; - rx_data[11: 0] <= {rx_data_0, rx_data_2}; + case (rx_frame) + 4'b1111: begin + rx_valid_r2 <= 1'b1; + rx_data_r2[23:12] <= {rx_data_1, rx_data_3}; + rx_data_r2[11: 0] <= {rx_data_0, rx_data_2}; end - 5'b01110: begin - rx_valid <= 1'b1; - rx_data[23:12] <= {rx_data_2, rx_data_s_0}; - rx_data[11: 0] <= {rx_data_1, rx_data_3}; + 4'b1110: begin + rx_valid_r2 <= 1'b1; + rx_data_r2[23:12] <= {rx_data_2, rx_data_0_s}; + rx_data_r2[11: 0] <= {rx_data_1, rx_data_3}; end - 5'b01100: begin - rx_valid <= 1'b1; - rx_data[23:12] <= {rx_data_3, rx_data_s_1}; - rx_data[11: 0] <= {rx_data_2, rx_data_s_0}; + 4'b1100: begin + rx_valid_r2 <= 1'b1; + rx_data_r2[23:12] <= {rx_data_3, rx_data_1_s}; + rx_data_r2[11: 0] <= {rx_data_2, rx_data_0_s}; end - 5'b01000: begin - rx_valid <= 1'b1; - rx_data[23:12] <= {rx_data_s_0, rx_data_s_2}; - rx_data[11: 0] <= {rx_data_3, rx_data_s_1}; + 4'b1000: begin + rx_valid_r2 <= 1'b1; + rx_data_r2[23:12] <= {rx_data_0_s, rx_data_2_s}; + rx_data_r2[11: 0] <= {rx_data_3, rx_data_1_s}; end - 5'b00000: begin - rx_valid <= 1'b0; - rx_data[23:12] <= {rx_data_1, rx_data_3}; - rx_data[11: 0] <= {rx_data_0, rx_data_2}; + 4'b0000: begin + rx_valid_r2 <= 1'b0; + rx_data_r2[23:12] <= {rx_data_1, rx_data_3}; + rx_data_r2[11: 0] <= {rx_data_0, rx_data_2}; end - 5'b00001: begin - rx_valid <= 1'b0; - rx_data[23:12] <= {rx_data_2, rx_data_s_0}; - rx_data[11: 0] <= {rx_data_1, rx_data_3}; + 4'b0001: begin + rx_valid_r2 <= 1'b0; + rx_data_r2[23:12] <= {rx_data_2, rx_data_0_s}; + rx_data_r2[11: 0] <= {rx_data_1, rx_data_3}; end - 5'b00011: begin - rx_valid <= 1'b0; - rx_data[23:12] <= {rx_data_3, rx_data_s_1}; - rx_data[11: 0] <= {rx_data_2, rx_data_s_0}; + 4'b0011: begin + rx_valid_r2 <= 1'b0; + rx_data_r2[23:12] <= {rx_data_3, rx_data_1_s}; + rx_data_r2[11: 0] <= {rx_data_2, rx_data_0_s}; end - 5'b00111: begin - rx_valid <= 1'b0; - rx_data[23:12] <= {rx_data_s_0, rx_data_s_2}; - rx_data[11: 0] <= {rx_data_3, rx_data_s_1}; - end - // R1 Mode - 5'b11100: begin - rx_valid <= 1'b0; - rx_data[23:12] <= {rx_data_s_1, rx_data_s_3}; - rx_data[11: 0] <= {rx_data_s_0, rx_data_s_2}; - end - 5'b10110: begin - rx_valid <= 1'b0; - rx_data[23:12] <= {rx_data_2, rx_data_s_0}; - rx_data[11: 0] <= {rx_data_1, rx_data_3}; - end - 5'b11001: begin - rx_valid <= 1'b0; - rx_data[23:12] <= {rx_data_s_0, rx_data_s_2}; - rx_data[11: 0] <= {rx_data_3, rx_data_s_1}; - end - 5'b10011: begin - rx_valid <= 1'b0; - rx_data[23:12] <= {rx_data_3, rx_data_s_1}; - rx_data[11: 0] <= {rx_data_2, rx_data_s_0}; + 4'b0111: begin + rx_valid_r2 <= 1'b0; + rx_data_r2[23:12] <= {rx_data_0_s, rx_data_2_s}; + rx_data_r2[11: 0] <= {rx_data_3, rx_data_1_s}; end default: begin - rx_valid <= 1'b0; - rx_data[23:12] <= 12'd0; - rx_data[11: 0] <= 12'd0; + rx_valid_r2 <= 1'b0; + rx_data_r2[23:12] <= 12'd0; + rx_data_r2[11: 0] <= 12'd0; end endcase - if (rx_valid == 1'b1) begin - adc_p_valid <= 1'b0; - adc_p_data <= {24'd0, rx_data}; + if (rx_valid_r2 == 1'b1) begin + adc_valid <= 1'b0; + adc_data <= {24'd0, rx_data_r2}; end else begin - adc_p_valid <= 1'b1; - adc_p_data <= (adc_r1_mode) ? {24'd0, rx_data} : {rx_data, adc_p_data[23:0]}; + adc_valid <= 1'b1; + adc_data <= {rx_data_r2, adc_data[23:0]}; end - adc_p_status <= ~rx_error & up_drp_locked; + adc_status <= ~rx_error_r2 & rx_locked_s & tx_locked_s; end - // transfer to a synchronous common clock - - always @(negedge l_clk) begin - adc_n_valid <= adc_p_valid; - adc_n_data <= adc_p_data; - adc_n_status <= adc_p_status; - end - - always @(posedge clk) begin - adc_valid <= adc_n_valid; - adc_data <= adc_n_data; - adc_status <= adc_n_status; - end - - always @(posedge clk) begin - if (dac_r1_mode == 1'b0) begin - tx_data_sel <= ~tx_data_sel; - end else begin - tx_data_sel <= 1'b0; - end - - case ({dac_r1_mode, tx_data_sel}) - 2'b10: begin - tx_frame <= 4'b1100; - tx_data_d_0 <= dac_data[11: 6]; // i msb - tx_data_d_1 <= dac_data[23:18]; // q msb - tx_data_d_2 <= dac_data[ 5: 0]; // i lsb - tx_data_d_3 <= dac_data[17:12]; // q lsb - end - 2'b00: begin - tx_frame <= 4'b1111; - tx_data_d_0 <= dac_data[11: 6]; // i msb 0 - tx_data_d_1 <= dac_data[23:18]; // q msb 0 - tx_data_d_2 <= dac_data[ 5: 0]; // i lsb 0 - tx_data_d_3 <= dac_data[17:12]; // q lsb 0 - end - 2'b01: begin - tx_frame <= 4'b0000; - tx_data_d_0 <= dac_data[35:30]; // i msb 1 - tx_data_d_1 <= dac_data[47:42]; // q msb 1 - tx_data_d_2 <= dac_data[29:24]; // i lsb 1 - tx_data_d_3 <= dac_data[41:36]; // q lsb 1 - end - endcase - - end - - // transfer data from a synchronous clock (skew less than 2ns) - - always @(negedge clk) begin - tx_n_frame <= tx_frame; - tx_n_data_d_0 <= tx_data_d_0; - tx_n_data_d_1 <= tx_data_d_1; - tx_n_data_d_2 <= tx_data_d_2; - tx_n_data_d_3 <= tx_data_d_3; - end + // transmit data path mux always @(posedge l_clk) begin - tx_p_frame <= tx_n_frame; - tx_p_data_d_0 <= tx_n_data_d_0; - tx_p_data_d_1 <= tx_n_data_d_1; - tx_p_data_d_2 <= tx_n_data_d_2; - tx_p_data_d_3 <= tx_n_data_d_3; - end - - // tdd/ensm control - - always @(posedge up_clk) begin - up_enable_int <= up_enable; - up_txnrx_int <= up_txnrx; - end - - always @(posedge clk or posedge rst) begin - if (rst == 1'b1) begin - enable_up_m1 <= 1'b0; - txnrx_up_m1 <= 1'b0; - enable_up <= 1'b0; - txnrx_up <= 1'b0; + tx_data_sel <= dac_valid; + tx_data <= dac_data; + if (tx_data_sel == 1'b1) begin + tx_frame <= 4'b1111; + tx_data_0 <= tx_data[11: 6]; + tx_data_1 <= tx_data[23:18]; + tx_data_2 <= tx_data[ 5: 0]; + tx_data_3 <= tx_data[17:12]; end else begin - enable_up_m1 <= up_enable_int; - txnrx_up_m1 <= up_txnrx_int; - enable_up <= enable_up_m1; - txnrx_up <= txnrx_up_m1; + tx_frame <= 4'b0000; + tx_data_0 <= tx_data[35:30]; + tx_data_1 <= tx_data[47:42]; + tx_data_2 <= tx_data[29:24]; + tx_data_3 <= tx_data[41:36]; end end - always @(posedge clk) begin - if (tdd_mode == 1'b1) begin - enable_int <= tdd_enable; - txnrx_int <= tdd_txnrx; - end else begin - enable_int <= enable_up; - txnrx_int <= txnrx_up; - end - end + // interface (transmit) - always @(negedge clk) begin - enable_n_int <= enable_int; - txnrx_n_int <= txnrx_int; - end + axi_ad9361_alt_lvds_tx i_tx ( + .tx_clk_out_p (tx_clk_out_p), + .tx_clk_out_n (tx_clk_out_n), + .tx_frame_out_p (tx_frame_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_clk (rx_clk_in_p), + .clk (l_clk), + .tx_frame (tx_frame), + .tx_data_0 (tx_data_0), + .tx_data_1 (tx_data_1), + .tx_data_2 (tx_data_2), + .tx_data_3 (tx_data_3), + .tx_locked (tx_locked_s)); - always @(posedge l_clk) begin - enable_p_int <= enable_n_int; - txnrx_p_int <= txnrx_n_int; - end + // interface (receive) - // receive data path interface - - ad_serdes_in #( - .DATA_WIDTH (6), - .SERDES_FACTOR (4), - .DEVICE_TYPE (DEVICE_TYPE)) - ad_serdes_data_in ( - .rst (mmcm_rst), - .clk (s_clk), - .div_clk (l_clk), - .loaden (loaden), - .locked (up_drp_locked), - .phase (phase_s), - .data_s0 (rx_data_s_0), - .data_s1 (rx_data_s_1), - .data_s2 (rx_data_s_2), - .data_s3 (rx_data_s_3), - .data_s4 (), - .data_s5 (), - .data_s6 (), - .data_s7 (), - .data_in_p (rx_data_in_p), - .data_in_n (rx_data_in_n), - .up_clk (1'd0), - .up_dld (6'd0), - .up_dwdata (30'd0), - .up_drdata (), - .delay_clk (1'd0), - .delay_rst (1'd0), - .delay_locked ()); - - // receive frame interface - - ad_serdes_in #( - .DATA_WIDTH (1), - .SERDES_FACTOR (4), - .DEVICE_TYPE (DEVICE_TYPE)) - ad_serdes_frame_in ( - .rst (mmcm_rst), - .clk (s_clk), - .div_clk (l_clk), - .loaden (loaden), - .locked (up_drp_locked), - .phase (phase_s), - .data_s0 (rx_frame_s[0]), - .data_s1 (rx_frame_s[1]), - .data_s2 (rx_frame_s[2]), - .data_s3 (rx_frame_s[3]), - .data_s4 (), - .data_s5 (), - .data_s6 (), - .data_s7 (), - .data_in_p (rx_frame_in_p), - .data_in_n (rx_frame_in_n), - .up_clk (1'd0), - .up_dld (1'd0), - .up_dwdata (5'd0), - .up_drdata (), - .delay_clk (1'd0), - .delay_rst (1'd0), - .delay_locked ()); - - // transmit data interface - - ad_serdes_out #( - .DATA_WIDTH (6), - .SERDES_FACTOR (4), - .DEVICE_TYPE (DEVICE_TYPE)) - ad_serdes_data_out ( - .rst (mmcm_rst), - .clk (s_clk), - .div_clk (l_clk), - .loaden (loaden), - .data_s0 (tx_p_data_d_0), - .data_s1 (tx_p_data_d_1), - .data_s2 (tx_p_data_d_2), - .data_s3 (tx_p_data_d_3), - .data_s4 (6'd0), - .data_s5 (6'd0), - .data_s6 (6'd0), - .data_s7 (6'd0), - .data_out_p (tx_data_out_p), - .data_out_n (tx_data_out_n)); - - // transmit frame interface - - ad_serdes_out #( - .DATA_WIDTH (1), - .SERDES_FACTOR (4), - .DEVICE_TYPE (DEVICE_TYPE)) - ad_serdes_frame_out ( - .rst (mmcm_rst), - .clk (s_clk), - .div_clk (l_clk), - .loaden (loaden), - .data_s0 (tx_p_frame[0]), - .data_s1 (tx_p_frame[1]), - .data_s2 (tx_p_frame[2]), - .data_s3 (tx_p_frame[3]), - .data_s4 (1'd0), - .data_s5 (1'd0), - .data_s6 (1'd0), - .data_s7 (1'd0), - .data_out_p (tx_frame_out_p), - .data_out_n (tx_frame_out_n)); - - // transmit clock interface - - ad_serdes_out #( - .DATA_WIDTH(1), - .SERDES_FACTOR(4), - .DEVICE_TYPE(DEVICE_TYPE)) - ad_serdes_tx_clock_out( - .rst (mmcm_rst), - .clk (s_clk), - .div_clk (l_clk), - .loaden (loaden), - .data_s0 (dac_clksel), - .data_s1 (~dac_clksel), - .data_s2 (dac_clksel), - .data_s3 (~dac_clksel), - .data_s4 (1'd0), - .data_s5 (1'd0), - .data_s6 (1'd0), - .data_s7 (1'd0), - .data_out_p (tx_clk_out_p), - .data_out_n (tx_clk_out_n)); - - // serdes clock interface - - ad_serdes_clk #( - .DEVICE_TYPE (DEVICE_TYPE)) - ad_serdes_clk ( - .rst (mmcm_rst), - .clk_in_p (rx_clk_in_p), - .clk_in_n (rx_clk_in_n), - .clk (s_clk), - .div_clk (l_clk), - .out_clk (), - .loaden (loaden), - .phase (phase_s), - .up_clk (up_clk), - .up_rstn (up_rstn), - .up_drp_sel (up_drp_sel), - .up_drp_wr (up_drp_wr), - .up_drp_addr (up_drp_addr), - .up_drp_wdata (up_drp_wdata), - .up_drp_rdata (up_drp_rdata), - .up_drp_ready (up_drp_ready), - .up_drp_locked (up_drp_locked)); - - // enable - - ad_cmos_out #( - .DEVICE_TYPE (DEVICE_TYPE)) - i_enable ( - .tx_clk (l_clk), - .tx_data_p (enable_p_int), - .tx_data_n (enable_p_int), - .tx_data_out (enable)); - - // txnrx - - ad_cmos_out #( - .DEVICE_TYPE (DEVICE_TYPE)) - i_txnrx ( - .tx_clk (l_clk), - .tx_data_p (txnrx_p_int), - .tx_data_n (txnrx_p_int), - .tx_data_out (txnrx)); + axi_ad9361_alt_lvds_rx i_rx ( + .rx_clk_in_p (rx_clk_in_p), + .rx_clk_in_n (rx_clk_in_n), + .rx_frame_in_p (rx_frame_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_data_in_n (rx_data_in_n), + .clk (l_clk), + .rx_frame (rx_frame_s), + .rx_data_0 (rx_data_0_s), + .rx_data_1 (rx_data_1_s), + .rx_data_2 (rx_data_2_s), + .rx_data_3 (rx_data_3_s), + .rx_locked (rx_locked_s)); endmodule diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl index eb936d355..3f8e62b56 100644 --- a/library/axi_ad9361/axi_ad9361_hw.tcl +++ b/library/axi_ad9361/axi_ad9361_hw.tcl @@ -5,9 +5,9 @@ source ../scripts/adi_ip_alt.tcl ad_ip_create axi_ad9361 {AXI AD9361 Interface} axi_ad9361_elab ad_ip_files axi_ad9361 [list\ - $ad_hdl_dir/library/altera/common/ad_cmos_out_core_c5.v \ - $ad_hdl_dir/library/altera/common/ad_serdes_in_core_c5.v \ - $ad_hdl_dir/library/altera/common/ad_serdes_out_core_c5.v \ + $ad_hdl_dir/library/altera/common/ad_lvds_clk.v \ + $ad_hdl_dir/library/altera/common/ad_lvds_in.v \ + $ad_hdl_dir/library/altera/common/ad_lvds_out.v \ $ad_hdl_dir/library/altera/common/ad_mul.v \ $ad_hdl_dir/library/altera/common/ad_dcfilter.v \ $ad_hdl_dir/library/common/ad_rst.v \ @@ -29,8 +29,9 @@ ad_ip_files axi_ad9361 [list\ $ad_hdl_dir/library/common/up_dac_common.v \ $ad_hdl_dir/library/common/up_dac_channel.v \ $ad_hdl_dir/library/common/up_tdd_cntrl.v \ + altera/axi_ad9361_alt_lvds_tx.v \ + altera/axi_ad9361_alt_lvds_rx.v \ altera/axi_ad9361_lvds_if.v \ - altera/axi_ad9361_cmos_if.v \ axi_ad9361_rx_pnmon.v \ axi_ad9361_rx_channel.v \ axi_ad9361_rx.v \ @@ -40,8 +41,7 @@ ad_ip_files axi_ad9361 [list\ axi_ad9361_tdd_if.v \ axi_ad9361.v \ $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc \ - axi_ad9361_constr.sdc] \ - axi_ad9361_fileset + axi_ad9361_constr.sdc] # parameters