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axi_fifo2s: include bus width/clock transfer

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Rejeesh Kutty 2014-11-11 15:25:47 -05:00
parent 9f2dbad539
commit 4381f20a6a
1 changed files with 7 additions and 3 deletions
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10
library/axi_fifo2s/axi_fifo2s_ip.tcl
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@ -6,7 +6,11 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_fifo2s
adi_ip_files axi_fifo2s [list \
"$ad_hdl_dir/library/common/ad_mem.v" \
"$ad_hdl_dir/library/common/ad_mem_asym.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
"axi_fifo2s_adc.v" \
"axi_fifo2s_dma.v" \
"axi_fifo2s_wr.v" \
"axi_fifo2s_rd.v" \
"axi_fifo2s.v" \
@ -17,9 +21,9 @@ adi_ip_constraints axi_fifo2s [list \
"axi_fifo2s_constr.xdc" ]
ipx::infer_bus_interfaces {{xilinx.com:interface:aximm:1.0}} [ipx::current_core]
ipx::remove_bus_interface {m} [ipx::current_core]
ipx::remove_bus_interface {m_signal_clock} [ipx::current_core]
ipx::remove_memory_map {m} [ipx::current_core]
#ipx::remove_bus_interface {m} [ipx::current_core]
#ipx::remove_bus_interface {m_signal_clock} [ipx::current_core]
#ipx::remove_memory_map {m} [ipx::current_core]
ipx::save_core [ipx::current_core]