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fmcomms11: Move project to a feature branch

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Istvan Csomortani 2018-04-13 12:53:50 +01:00 committed by István Csomortáni
parent 6419de60c4
commit 43496cf80a
8 changed files with 0 additions and 730 deletions
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projects/fmcomms11/Makefile
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
include ../scripts/project-toplevel.mk

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projects/fmcomms11/common/fmcomms11_bd.tcl
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
# dac peripherals
ad_ip_instance axi_adxcvr axi_ad9162_xcvr
ad_ip_parameter axi_ad9162_xcvr CONFIG.NUM_OF_LANES 8
ad_ip_parameter axi_ad9162_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_ad9162_xcvr CONFIG.TX_OR_RX_N 1
ad_ip_instance axi_ad9162 axi_ad9162_core
adi_axi_jesd204_tx_create axi_ad9162_jesd 8
ad_ip_instance axi_dmac axi_ad9162_dma
ad_ip_parameter axi_ad9162_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_ad9162_dma CONFIG.DMA_TYPE_DEST 1
ad_ip_parameter axi_ad9162_dma CONFIG.ID 1
ad_ip_parameter axi_ad9162_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9162_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad9162_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_ad9162_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9162_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9162_dma CONFIG.DMA_DATA_WIDTH_SRC 256
ad_ip_parameter axi_ad9162_dma CONFIG.DMA_DATA_WIDTH_DEST 256
# adc peripherals
ad_ip_instance axi_adxcvr axi_ad9625_xcvr
ad_ip_parameter axi_ad9625_xcvr CONFIG.NUM_OF_LANES 8
ad_ip_parameter axi_ad9625_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_ad9625_xcvr CONFIG.TX_OR_RX_N 0
ad_ip_instance axi_ad9625 axi_ad9625_core
adi_axi_jesd204_rx_create axi_ad9625_jesd 8
ad_ip_instance axi_dmac axi_ad9625_dma
ad_ip_parameter axi_ad9625_dma CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_ad9625_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad9625_dma CONFIG.ID 0
ad_ip_parameter axi_ad9625_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9625_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad9625_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_ad9625_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_ad9625_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9625_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9625_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter axi_ad9625_dma CONFIG.DMA_DATA_WIDTH_DEST 64
# shared transceiver core
ad_ip_instance util_adxcvr util_fmcomms11_xcvr
ad_ip_parameter util_fmcomms11_xcvr CONFIG.QPLL_FBDIV 0x120
ad_ip_parameter util_fmcomms11_xcvr CONFIG.CPLL_FBDIV 4
ad_ip_parameter util_fmcomms11_xcvr CONFIG.TX_NUM_OF_LANES 8
ad_ip_parameter util_fmcomms11_xcvr CONFIG.TX_CLK25_DIV 7
ad_ip_parameter util_fmcomms11_xcvr CONFIG.RX_NUM_OF_LANES 8
ad_ip_parameter util_fmcomms11_xcvr CONFIG.RX_CLK25_DIV 7
ad_ip_parameter util_fmcomms11_xcvr CONFIG.RX_DFE_LPM_CFG 0x0904
ad_ip_parameter util_fmcomms11_xcvr CONFIG.RX_CDR_CFG 0x03000023ff10400020
# reference clocks & resets
create_bd_port -dir I tx_ref_clk_0
create_bd_port -dir I rx_ref_clk_0
ad_xcvrpll tx_ref_clk_0 util_fmcomms11_xcvr/qpll_ref_clk_*
ad_xcvrpll rx_ref_clk_0 util_fmcomms11_xcvr/cpll_ref_clk_*
ad_xcvrpll axi_ad9162_xcvr/up_pll_rst util_fmcomms11_xcvr/up_qpll_rst_*
ad_xcvrpll axi_ad9625_xcvr/up_pll_rst util_fmcomms11_xcvr/up_cpll_rst_*
ad_connect sys_cpu_resetn util_fmcomms11_xcvr/up_rstn
ad_connect sys_cpu_clk util_fmcomms11_xcvr/up_clk
# connections (dac)
ad_xcvrcon util_fmcomms11_xcvr axi_ad9162_xcvr axi_ad9162_jesd
ad_connect util_fmcomms11_xcvr/tx_out_clk_0 axi_ad9162_core/tx_clk
ad_connect axi_ad9162_jesd/tx_data_tdata axi_ad9162_core/tx_data
ad_connect util_fmcomms11_xcvr/tx_out_clk_0 axi_ad9162_fifo/dac_clk
ad_connect axi_ad9162_core/dac_valid axi_ad9162_fifo/dac_valid
ad_connect axi_ad9162_core/dac_ddata axi_ad9162_fifo/dac_data
ad_connect axi_ad9162_core/dac_dunf axi_ad9162_fifo/dac_dunf
ad_connect axi_ad9162_jesd_rstgen/peripheral_reset axi_ad9162_fifo/dac_rst
ad_connect sys_cpu_clk axi_ad9162_fifo/dma_clk
ad_connect sys_cpu_reset axi_ad9162_fifo/dma_rst
ad_connect sys_cpu_clk axi_ad9162_dma/m_axis_aclk
ad_connect sys_cpu_resetn axi_ad9162_dma/m_src_axi_aresetn
ad_connect axi_ad9162_fifo/dma_xfer_req axi_ad9162_dma/m_axis_xfer_req
ad_connect axi_ad9162_fifo/dma_ready axi_ad9162_dma/m_axis_ready
ad_connect axi_ad9162_fifo/dma_data axi_ad9162_dma/m_axis_data
ad_connect axi_ad9162_fifo/dma_valid axi_ad9162_dma/m_axis_valid
ad_connect axi_ad9162_fifo/dma_xfer_last axi_ad9162_dma/m_axis_last
# connections (adc)
ad_xcvrcon util_fmcomms11_xcvr axi_ad9625_xcvr axi_ad9625_jesd
ad_connect util_fmcomms11_xcvr/rx_out_clk_0 axi_ad9625_core/rx_clk
ad_connect axi_ad9625_jesd/rx_sof axi_ad9625_core/rx_sof
ad_connect axi_ad9625_jesd/rx_data_tdata axi_ad9625_core/rx_data
ad_connect util_fmcomms11_xcvr/rx_out_clk_0 axi_ad9625_fifo/adc_clk
ad_connect axi_ad9625_jesd_rstgen/peripheral_reset axi_ad9625_fifo/adc_rst
ad_connect axi_ad9625_core/adc_valid axi_ad9625_fifo/adc_wr
ad_connect axi_ad9625_core/adc_data axi_ad9625_fifo/adc_wdata
ad_connect sys_cpu_clk axi_ad9625_fifo/dma_clk
ad_connect sys_cpu_clk axi_ad9625_dma/s_axis_aclk
ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn
ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid
ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data
ad_connect axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready
ad_connect axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req
ad_connect axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf
# interconnect (cpu)
ad_cpu_interconnect 0x44A60000 axi_ad9162_xcvr
ad_cpu_interconnect 0x44A00000 axi_ad9162_core
ad_cpu_interconnect 0x44A90000 axi_ad9162_jesd
ad_cpu_interconnect 0x7c420000 axi_ad9162_dma
ad_cpu_interconnect 0x44A50000 axi_ad9625_xcvr
ad_cpu_interconnect 0x44A10000 axi_ad9625_core
ad_cpu_interconnect 0x44AA0000 axi_ad9625_jesd
ad_cpu_interconnect 0x7c400000 axi_ad9625_dma
# gt uses hp3, and 100MHz clock for both DRP and AXI4
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9625_xcvr/m_axi
# interconnect (mem/dac)
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_cpu_clk axi_ad9162_dma/m_src_axi
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_cpu_clk axi_ad9625_dma/m_dest_axi
# interrupts
ad_cpu_interrupt ps-10 mb-15 axi_ad9162_jesd/irq
ad_cpu_interrupt ps-11 mb-14 axi_ad9625_jesd/irq
ad_cpu_interrupt ps-12 mb-12 axi_ad9162_dma/irq
ad_cpu_interrupt ps-13 mb-13 axi_ad9625_dma/irq
# unused
ad_connect axi_ad9162_fifo/bypass GND

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projects/fmcomms11/common/fmcomms11_spi.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module fmcomms11_spi (
// 4 wire
input [ 2:0] spi_csn,
input spi_clk,
input spi_mosi,
output spi_miso,
// 3 wire
output spi_csn_ad9625,
output spi_csn_ad9162,
output spi_csn_ad9508,
output spi_csn_adl5240,
output spi_csn_adf4355,
output spi_csn_hmc1119,
inout spi_sdio,
output spi_dir);
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire [ 5:0] spi_csn6_s;
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_ad9625 = spi_csn6_s[0];
assign spi_csn_ad9162 = spi_csn6_s[1];
assign spi_csn_ad9508 = spi_csn6_s[2];
assign spi_csn_adl5240 = spi_csn6_s[3];
assign spi_csn_adf4355 = spi_csn6_s[4];
assign spi_csn_hmc1119 = spi_csn6_s[5];
assign spi_csn6_s[0] = (spi_csn == 3'b001) ? 1'b0 : 1'b1;
assign spi_csn6_s[1] = (spi_csn == 3'b010) ? 1'b0 : 1'b1;
assign spi_csn6_s[2] = (spi_csn == 3'b011) ? 1'b0 : 1'b1;
assign spi_csn6_s[3] = (spi_csn == 3'b100) ? 1'b0 : 1'b1;
assign spi_csn6_s[4] = (spi_csn == 3'b101) ? 1'b0 : 1'b1;
assign spi_csn6_s[5] = (spi_csn == 3'b110) ? 1'b0 : 1'b1;
assign spi_csn_s = & spi_csn6_s;
assign spi_dir = ~spi_enable_s;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io buffer
assign spi_miso = spi_sdio;
assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
endmodule
// ***************************************************************************
// ***************************************************************************

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projects/fmcomms11/zc706/Makefile
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := fmcomms11_zc706
M_DEPS += ../common/fmcomms11_spi.v
M_DEPS += ../common/fmcomms11_bd.tcl
M_DEPS += ../../common/zc706/zc706_system_constr.xdc
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
M_DEPS += ../../common/zc706/zc706_plddr3_constr.xdc
M_DEPS += ../../common/zc706/zc706_plddr3_adcfifo_bd.tcl
M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
LIB_DEPS += axi_ad9162
LIB_DEPS += axi_ad9625
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_spdif_tx
LIB_DEPS += jesd204/axi_jesd204_rx
LIB_DEPS += jesd204/axi_jesd204_tx
LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += jesd204/jesd204_tx
LIB_DEPS += util_dacfifo
LIB_DEPS += xilinx/axi_adcfifo
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr
include ../../scripts/project-xilinx.mk

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projects/fmcomms11/zc706/system_bd.tcl
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set adc_fifo_name axi_ad9625_fifo
set adc_fifo_address_width 18
set adc_data_width 256
set adc_dma_data_width 64
set dac_fifo_name axi_ad9162_fifo
set dac_fifo_address_width 10
set dac_data_width 256
set dac_dma_data_width 256
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
source ../common/fmcomms11_bd.tcl

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projects/fmcomms11/zc706/system_constr.xdc
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# fmcomms11
set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P
set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N
set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P
set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N
set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P
set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N
set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P
set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN AD6 } [get_ports rx_data_p[4]] ; ## B12 FMC_HPC_DP7_M2C_P
set_property -dict {PACKAGE_PIN AD5 } [get_ports rx_data_n[4]] ; ## B13 FMC_HPC_DP7_M2C_N
set_property -dict {PACKAGE_PIN AH6 } [get_ports rx_data_p[5]] ; ## A14 FMC_HPC_DP4_M2C_P
set_property -dict {PACKAGE_PIN AH5 } [get_ports rx_data_n[5]] ; ## A15 FMC_HPC_DP4_M2C_N
set_property -dict {PACKAGE_PIN AF6 } [get_ports rx_data_p[6]] ; ## B16 FMC_HPC_DP6_M2C_P
set_property -dict {PACKAGE_PIN AF5 } [get_ports rx_data_n[6]] ; ## B17 FMC_HPC_DP6_M2C_N
set_property -dict {PACKAGE_PIN AG4 } [get_ports rx_data_p[7]] ; ## A18 FMC_HPC_DP5_M2C_P
set_property -dict {PACKAGE_PIN AG3 } [get_ports rx_data_n[7]] ; ## A19 FMC_HPC_DP5_M2C_N
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## H07 FMC_HPC_LA02_P
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## H08 FMC_HPC_LA02_N
set_property -dict {PACKAGE_PIN AD10} [get_ports trx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
set_property -dict {PACKAGE_PIN AD9 } [get_ports trx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[0]] ; ## C02 FMC_HPC_DP0_C2M_P
set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[0]] ; ## C03 FMC_HPC_DP0_C2M_N
set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[1]] ; ## A22 FMC_HPC_DP1_C2M_P
set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[1]] ; ## A23 FMC_HPC_DP1_C2M_N
set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P
set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N
set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[3]] ; ## A30 FMC_HPC_DP3_C2M_P
set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[3]] ; ## A31 FMC_HPC_DP3_C2M_N
set_property -dict {PACKAGE_PIN AD2 } [get_ports tx_data_p[4]] ; ## B32 FMC_HPC_DP7_C2M_P
set_property -dict {PACKAGE_PIN AD1 } [get_ports tx_data_n[4]] ; ## B33 FMC_HPC_DP7_C2M_N
set_property -dict {PACKAGE_PIN AH2 } [get_ports tx_data_p[5]] ; ## A34 FMC_HPC_DP4_C2M_P
set_property -dict {PACKAGE_PIN AH1 } [get_ports tx_data_n[5]] ; ## A35 FMC_HPC_DP4_C2M_N
set_property -dict {PACKAGE_PIN AE4 } [get_ports tx_data_p[6]] ; ## B36 FMC_HPC_DP6_C2M_P
set_property -dict {PACKAGE_PIN AE3 } [get_ports tx_data_n[6]] ; ## B37 FMC_HPC_DP6_C2M_N
set_property -dict {PACKAGE_PIN AF2 } [get_ports tx_data_p[7]] ; ## A38 FMC_HPC_DP5_C2M_P
set_property -dict {PACKAGE_PIN AF1 } [get_ports tx_data_n[7]] ; ## A39 FMC_HPC_DP5_C2M_N
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## G09 FMC_HPC_LA03_P
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## G10 FMC_HPC_LA03_N
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports usr_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports usr_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9625] ; ## C11 FMC_HPC_LA06_N
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9162] ; ## G12 FMC_HPC_LA08_P
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9508] ; ## H14 FMC_HPC_LA07_N
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports spi_csn_adl5240] ; ## C10 FMC_HPC_LA06_P
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports spi_csn_adf4355] ; ## G16 FMC_HPC_LA12_N
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports spi_csn_hmc1119] ; ## G15 FMC_HPC_LA12_P
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## C14 FMC_HPC_LA10_P
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## C15 FMC_HPC_LA10_N
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports spi_dir] ; ## H13 FMC_HPC_LA07_P
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports adf4355_muxout] ; ## D14 FMC_HPC_LA09_P
set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports ad9162_txen] ; ## G13 FMC_HPC_LA08_N
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports ad9625_irq] ; ## D15 FMC_HPC_LA09_N
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports ad9162_irq] ; ## H16 FMC_HPC_LA11_P
# clocks
create_clock -name rx_ref_clk -period 6.40 [get_ports trx_ref_clk_p]
create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_fmcomms11_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcomms11_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]

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projects/fmcomms11/zc706/system_project.tcl
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_xilinx fmcomms11_zc706
adi_project_files fmcomms11_zc706 [list \
"../common/fmcomms11_spi.v" \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zc706/zc706_plddr3_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
set_property part "xc7z045ffg900-3" [get_runs synth_1]
set_property part "xc7z045ffg900-3" [get_runs impl_1]
adi_project_run fmcomms11_zc706

324
projects/fmcomms11/zc706/system_top.v
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@ -1,324 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [14:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [23:0] hdmi_data,
output spdif,
input sys_rst,
input sys_clk_p,
input sys_clk_n,
output [13:0] ddr3_addr,
output [ 2:0] ddr3_ba,
output ddr3_cas_n,
output [ 0:0] ddr3_ck_n,
output [ 0:0] ddr3_ck_p,
output [ 0:0] ddr3_cke,
output [ 0:0] ddr3_cs_n,
output [ 7:0] ddr3_dm,
inout [63:0] ddr3_dq,
inout [ 7:0] ddr3_dqs_n,
inout [ 7:0] ddr3_dqs_p,
output [ 0:0] ddr3_odt,
output ddr3_ras_n,
output ddr3_reset_n,
output ddr3_we_n,
inout iic_scl,
inout iic_sda,
output rx_sync_p,
output rx_sync_n,
input [ 7:0] rx_data_p,
input [ 7:0] rx_data_n,
input trx_ref_clk_p,
input trx_ref_clk_n,
input tx_sync_p,
input tx_sync_n,
output [ 7:0] tx_data_p,
output [ 7:0] tx_data_n,
input usr_clk_p,
input usr_clk_n,
inout adf4355_muxout,
inout ad9162_txen,
inout ad9625_irq,
inout ad9162_irq,
output spi_csn_ad9625,
output spi_csn_ad9162,
output spi_csn_ad9508,
output spi_csn_adl5240,
output spi_csn_adf4355,
output spi_csn_hmc1119,
output spi_clk,
inout spi_sdio,
output spi_dir);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire [ 2:0] spi1_csn;
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
wire rx_sync;
wire trx_ref_clk;
wire tx_sync;
wire usr_clk;
// instantiations
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
IBUFDS_GTE2 i_ibufds_tx_ref_clk (
.CEB (1'd0),
.I (trx_ref_clk_p),
.IB (trx_ref_clk_n),
.O (trx_ref_clk),
.ODIV2 ());
IBUFDS i_ibufds_tx_sync (
.I (tx_sync_p),
.IB (tx_sync_n),
.O (tx_sync));
IBUFDS i_ibufds_usr_clk (
.I (usr_clk_p),
.IB (usr_clk_n),
.O (usr_clk));
fmcomms11_spi i_spi (
.spi_csn (spi0_csn),
.spi_clk (spi_clk),
.spi_mosi (spi0_mosi),
.spi_miso (spi0_miso),
.spi_csn_ad9625 (spi_csn_ad9625),
.spi_csn_ad9162 (spi_csn_ad9162),
.spi_csn_ad9508 (spi_csn_ad9508),
.spi_csn_adl5240 (spi_csn_adl5240),
.spi_csn_adf4355 (spi_csn_adf4355),
.spi_csn_hmc1119 (spi_csn_hmc1119),
.spi_sdio (spi_sdio),
.spi_dir (spi_dir));
assign spi_clk = spi0_clk;
assign gpio_i[63:36] = gpio_o[63:36];
ad_iobuf #(.DATA_WIDTH(4)) i_iobuf (
.dio_t ({gpio_t[35:32]}),
.dio_i ({gpio_o[35:32]}),
.dio_o ({gpio_i[35:32]}),
.dio_p ({ adf4355_muxout, // 35
ad9162_txen, // 34
ad9625_irq, // 33
ad9162_irq})); // 32
assign gpio_i[31:15] = gpio_o[31:15];
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.rx_data_0_n (rx_data_n[0]),
.rx_data_0_p (rx_data_p[0]),
.rx_data_1_n (rx_data_n[1]),
.rx_data_1_p (rx_data_p[1]),
.rx_data_2_n (rx_data_n[2]),
.rx_data_2_p (rx_data_p[2]),
.rx_data_3_n (rx_data_n[3]),
.rx_data_3_p (rx_data_p[3]),
.rx_data_4_n (rx_data_n[4]),
.rx_data_4_p (rx_data_p[4]),
.rx_data_5_n (rx_data_n[5]),
.rx_data_5_p (rx_data_p[5]),
.rx_data_6_n (rx_data_n[6]),
.rx_data_6_p (rx_data_p[6]),
.rx_data_7_n (rx_data_n[7]),
.rx_data_7_p (rx_data_p[7]),
.rx_ref_clk_0 (trx_ref_clk),
.rx_sync_0 (rx_sync),
.rx_sysref_0 (1'b0),
.spdif (spdif),
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),
.spi0_csn_0_o (spi0_csn[0]),
.spi0_csn_1_o (spi0_csn[1]),
.spi0_csn_2_o (spi0_csn[2]),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi0_miso),
.spi0_sdo_i (spi0_mosi),
.spi0_sdo_o (spi0_mosi),
.spi1_clk_i (spi1_clk),
.spi1_clk_o (spi1_clk),
.spi1_csn_0_o (spi1_csn[0]),
.spi1_csn_1_o (spi1_csn[1]),
.spi1_csn_2_o (spi1_csn[2]),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b1),
.spi1_sdo_i (spi1_mosi),
.spi1_sdo_o (spi1_mosi),
.sys_clk_clk_n (sys_clk_n),
.sys_clk_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.tx_data_0_n (tx_data_n[0]),
.tx_data_0_p (tx_data_p[0]),
.tx_data_1_n (tx_data_n[1]),
.tx_data_1_p (tx_data_p[1]),
.tx_data_2_n (tx_data_n[2]),
.tx_data_2_p (tx_data_p[2]),
.tx_data_3_n (tx_data_n[3]),
.tx_data_3_p (tx_data_p[3]),
.tx_data_4_n (tx_data_n[4]),
.tx_data_4_p (tx_data_p[4]),
.tx_data_5_n (tx_data_n[5]),
.tx_data_5_p (tx_data_p[5]),
.tx_data_6_n (tx_data_n[6]),
.tx_data_6_p (tx_data_p[6]),
.tx_data_7_n (tx_data_n[7]),
.tx_data_7_p (tx_data_p[7]),
.tx_ref_clk_0 (trx_ref_clk),
.tx_sync_0 (tx_sync),
.tx_sysref_0 (1'b0));
endmodule
// ***************************************************************************
// ***************************************************************************