From 42abe0cf46c910ef2d59a1f8876eb35b725097df Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Wed, 6 Jun 2018 12:24:47 +0300 Subject: [PATCH] axi_ad9361: Updates for ad_dds phase acc wrapper --- library/axi_ad9361/Makefile | 3 + library/axi_ad9361/axi_ad9361.v | 10 ++-- library/axi_ad9361/axi_ad9361_hw.tcl | 1 + library/axi_ad9361/axi_ad9361_ip.tcl | 1 + library/axi_ad9361/axi_ad9361_tx.v | 37 ++++++------ library/axi_ad9361/axi_ad9361_tx_channel.v | 66 +++++++++------------- 6 files changed, 58 insertions(+), 60 deletions(-) diff --git a/library/axi_ad9361/Makefile b/library/axi_ad9361/Makefile index e880a879c..5f239f25a 100644 --- a/library/axi_ad9361/Makefile +++ b/library/axi_ad9361/Makefile @@ -9,7 +9,10 @@ GENERIC_DEPS += ../common/ad_addsub.v GENERIC_DEPS += ../common/ad_datafmt.v GENERIC_DEPS += ../common/ad_dds.v GENERIC_DEPS += ../common/ad_dds_1.v +GENERIC_DEPS += ../common/ad_dds_2.v +GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v GENERIC_DEPS += ../common/ad_dds_sine.v +GENERIC_DEPS += ../common/ad_dds_sine_cordic.v GENERIC_DEPS += ../common/ad_iqcor.v GENERIC_DEPS += ../common/ad_pnmon.v GENERIC_DEPS += ../common/ad_pps_receiver.v diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v index 7028230f9..fac7dab0d 100644 --- a/library/axi_ad9361/axi_ad9361.v +++ b/library/axi_ad9361/axi_ad9361.v @@ -57,7 +57,8 @@ module axi_ad9361 #( parameter DAC_DATAPATH_DISABLE = 0, parameter DAC_DDS_DISABLE = 0, parameter DAC_DDS_TYPE = 1, - parameter DAC_DDS_CORDIC_DW = 16, + parameter DAC_DDS_CORDIC_DW = 14, + parameter DAC_DDS_CORDIC_PHASE_DW = 13, parameter DAC_USERPORTS_DISABLE = 0, parameter DAC_IQCORRECTION_DISABLE = 0, parameter IO_DELAY_GROUP = "dev_if_delay_group") ( @@ -635,9 +636,10 @@ module axi_ad9361 #( .CMOS_OR_LVDS_N (CMOS_OR_LVDS_N), .PPS_RECEIVER_ENABLE (PPS_RECEIVER_ENABLE), .INIT_DELAY (DAC_INIT_DELAY), - .DDS_DISABLE (DAC_DDS_DISABLE_INT), - .DDS_TYPE (DAC_DDS_TYPE), - .CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_DISABLE (DAC_DDS_DISABLE_INT), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .USERPORTS_DISABLE (DAC_USERPORTS_DISABLE_INT), .DELAYCNTRL_DISABLE (DAC_DELAYCNTRL_DISABLE_INT), .IQCORRECTION_DISABLE (DAC_IQCORRECTION_DISABLE_INT)) diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl index dace36789..d493bd4f5 100644 --- a/library/axi_ad9361/axi_ad9361_hw.tcl +++ b/library/axi_ad9361/axi_ad9361_hw.tcl @@ -12,6 +12,7 @@ ad_ip_files axi_ad9361 [list\ $ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \ $ad_hdl_dir/library/common/ad_dds_sine_cordic.v \ $ad_hdl_dir/library/common/ad_dds_sine.v \ + $ad_hdl_dir/library/common/ad_dds_2.v \ $ad_hdl_dir/library/common/ad_dds_1.v \ $ad_hdl_dir/library/common/ad_dds.v \ $ad_hdl_dir/library/common/ad_datafmt.v \ diff --git a/library/axi_ad9361/axi_ad9361_ip.tcl b/library/axi_ad9361/axi_ad9361_ip.tcl index 1d5f38e81..0fc681693 100644 --- a/library/axi_ad9361/axi_ad9361_ip.tcl +++ b/library/axi_ad9361/axi_ad9361_ip.tcl @@ -15,6 +15,7 @@ adi_ip_files axi_ad9361 [list \ "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ "$ad_hdl_dir/library/common/ad_dds_sine.v" \ + "$ad_hdl_dir/library/common/ad_dds_2.v" \ "$ad_hdl_dir/library/common/ad_dds_1.v" \ "$ad_hdl_dir/library/common/ad_dds.v" \ "$ad_hdl_dir/library/common/ad_datafmt.v" \ diff --git a/library/axi_ad9361/axi_ad9361_tx.v b/library/axi_ad9361/axi_ad9361_tx.v index bc6433955..83959c23b 100644 --- a/library/axi_ad9361/axi_ad9361_tx.v +++ b/library/axi_ad9361/axi_ad9361_tx.v @@ -45,9 +45,10 @@ module axi_ad9361_tx #( parameter CMOS_OR_LVDS_N = 0, parameter PPS_RECEIVER_ENABLE = 0, parameter INIT_DELAY = 0, - parameter DDS_DISABLE = 0, - parameter DDS_TYPE = 1, - parameter CORDIC_DW = 16, + parameter DAC_DDS_DISABLE = 0, + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_CORDIC_DW = 14, + parameter DAC_DDS_CORDIC_PHASE_DW = 13, parameter USERPORTS_DISABLE = 0, parameter DELAYCNTRL_DISABLE = 0, parameter IQCORRECTION_DISABLE = 0) ( @@ -119,7 +120,7 @@ module axi_ad9361_tx #( localparam CONFIG = (PPS_RECEIVER_ENABLE * 256) + (CMOS_OR_LVDS_N * 128) + - (DDS_DISABLE * 64) + + (DAC_DDS_DISABLE * 64) + (DELAYCNTRL_DISABLE * 32) + (MODE_1R1T * 16) + (USERPORTS_DISABLE * 8) + @@ -215,9 +216,10 @@ module axi_ad9361_tx #( .CHANNEL_ID (0), .Q_OR_I_N (0), .DISABLE (0), - .DDS_DISABLE (DDS_DISABLE), - .DDS_TYPE (DDS_TYPE), - .CORDIC_DW (CORDIC_DW), + .DAC_DDS_DISABLE (DAC_DDS_DISABLE), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .USERPORTS_DISABLE (USERPORTS_DISABLE), .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) i_tx_channel_0 ( @@ -249,9 +251,10 @@ module axi_ad9361_tx #( .CHANNEL_ID (1), .Q_OR_I_N (1), .DISABLE (0), - .DDS_DISABLE (DDS_DISABLE), - .DDS_TYPE (DDS_TYPE), - .CORDIC_DW (CORDIC_DW), + .DAC_DDS_DISABLE (DAC_DDS_DISABLE), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .USERPORTS_DISABLE (USERPORTS_DISABLE), .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) i_tx_channel_1 ( @@ -283,9 +286,10 @@ module axi_ad9361_tx #( .CHANNEL_ID (2), .Q_OR_I_N (0), .DISABLE (MODE_1R1T), - .DDS_DISABLE (DDS_DISABLE), - .DDS_TYPE (DDS_TYPE), - .CORDIC_DW (CORDIC_DW), + .DAC_DDS_DISABLE (DAC_DDS_DISABLE), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .USERPORTS_DISABLE (USERPORTS_DISABLE), .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) i_tx_channel_2 ( @@ -317,9 +321,10 @@ module axi_ad9361_tx #( .CHANNEL_ID (3), .Q_OR_I_N (1), .DISABLE (MODE_1R1T), - .DDS_DISABLE (DDS_DISABLE), - .DDS_TYPE (DDS_TYPE), - .CORDIC_DW (CORDIC_DW), + .DAC_DDS_DISABLE (DAC_DDS_DISABLE), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .USERPORTS_DISABLE (USERPORTS_DISABLE), .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) i_tx_channel_3 ( diff --git a/library/axi_ad9361/axi_ad9361_tx_channel.v b/library/axi_ad9361/axi_ad9361_tx_channel.v index 36e99789d..f85d7588f 100644 --- a/library/axi_ad9361/axi_ad9361_tx_channel.v +++ b/library/axi_ad9361/axi_ad9361_tx_channel.v @@ -42,9 +42,10 @@ module axi_ad9361_tx_channel #( parameter Q_OR_I_N = 0, parameter CHANNEL_ID = 32'h0, parameter DISABLE = 0, - parameter DDS_DISABLE = 0, - parameter DDS_TYPE = 1, - parameter CORDIC_DW = 16, + parameter DAC_DDS_DISABLE = 0, + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_CORDIC_DW = 14, + parameter DAC_DDS_CORDIC_PHASE_DW = 13, parameter USERPORTS_DISABLE = 0, parameter IQCORRECTION_DISABLE = 0) ( @@ -95,17 +96,12 @@ module axi_ad9361_tx_channel #( reg [23:0] dac_pn_seq = 'd0; reg [11:0] dac_pn_data = 'd0; reg [15:0] dac_pat_data = 'd0; - reg [15:0] dac_dds_phase_0 = 'd0; - reg [15:0] dac_dds_phase_1 = 'd0; - reg [15:0] dac_dds_incr_0 = 'd0; - reg [15:0] dac_dds_incr_1 = 'd0; - reg [15:0] dac_dds_data = 'd0; // internal signals wire dac_iqcor_valid_s; wire [15:0] dac_iqcor_data_s; - wire [15:0] dac_dds_data_s; + wire [11:0] dac_dds_data_s; wire [15:0] dac_dds_scale_1_s; wire [15:0] dac_dds_init_1_s; wire [15:0] dac_dds_incr_1_s; @@ -285,7 +281,7 @@ module axi_ad9361_tx_channel #( 4'h3: dac_data_out_int <= 12'd0; 4'h2: dac_data_out_int <= dma_data[15:4]; 4'h1: dac_data_out_int <= dac_pat_data[15:4]; - default: dac_data_out_int <= dac_dds_data[15:4]; + default: dac_data_out_int <= dac_dds_data_s; endcase end @@ -305,7 +301,7 @@ module axi_ad9361_tx_channel #( end end end - + // pattern always @(posedge dac_clk) begin @@ -320,36 +316,26 @@ module axi_ad9361_tx_channel #( // dds - always @(posedge dac_clk) begin - if (dac_data_sync == 1'b1) begin - dac_dds_phase_0 <= dac_dds_init_1_s; - dac_dds_phase_1 <= dac_dds_init_2_s; - dac_dds_incr_0 <= dac_dds_incr_1_s; - dac_dds_incr_1 <= dac_dds_incr_2_s; - dac_dds_data <= 16'd0; - end else if (dac_valid == 1'b1) begin - dac_dds_phase_0 <= dac_dds_phase_0 + dac_dds_incr_0; - dac_dds_phase_1 <= dac_dds_phase_1 + dac_dds_incr_1; - dac_dds_incr_0 <= dac_dds_incr_0; - dac_dds_incr_1 <= dac_dds_incr_1; - dac_dds_data <= dac_dds_data_s; - end - end - - // dds - ad_dds #( - .DDS_TYPE (DDS_TYPE), - .CORDIC_DW (CORDIC_DW), - .DISABLE (DDS_DISABLE)) + .DISABLE (DAC_DDS_DISABLE), + .DDS_DW (12), + .PHASE_DW (16), + .DDS_TYPE (DAC_DDS_TYPE), + .CORDIC_DW (DAC_DDS_CORDIC_DW), + .CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .CLK_RATIO (1)) i_dds ( .clk (dac_clk), - .dds_format (dac_dds_format), - .dds_phase_0 (dac_dds_phase_0), - .dds_scale_0 (dac_dds_scale_1_s), - .dds_phase_1 (dac_dds_phase_1), - .dds_scale_1 (dac_dds_scale_2_s), - .dds_data (dac_dds_data_s)); + .dac_dds_format (dac_dds_format), + .dac_data_sync (dac_data_sync), + .dac_valid (dac_valid), + .tone_1_scale (dac_dds_scale_1_s), + .tone_2_scale (dac_dds_scale_2_s), + .tone_1_init_offset (dac_dds_init_1_s), + .tone_2_init_offset (dac_dds_init_2_s), + .tone_1_freq_word (dac_dds_incr_1_s), + .tone_2_freq_word (dac_dds_incr_2_s), + .dac_dds_data (dac_dds_data_s)); // single channel processor @@ -360,7 +346,7 @@ module axi_ad9361_tx_channel #( up_dac_channel #( .COMMON_ID (6'h11), .CHANNEL_ID (CHANNEL_ID), - .DDS_DISABLE (DDS_DISABLE), + .DDS_DISABLE (DAC_DDS_DISABLE), .USERPORTS_DISABLE (USERPORTS_DISABLE), .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) i_up_dac_channel ( @@ -403,7 +389,7 @@ module axi_ad9361_tx_channel #( .up_raddr (up_raddr), .up_rdata (up_rdata_s), .up_rack (up_rack_s)); - + endmodule // ***************************************************************************