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prcfg_library: Major update 

Get rid of the QPSK symbol wrapper for now. The DMA data path is using the 2 LSB bits.
main
Istvan Csomortani 2014-11-14 17:54:00 +02:00
parent 5c7e8eb926
commit 42874bfe81
5 changed files with 76 additions and 154 deletions
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47
library/prcfg/bist/prcfg_adc.v
View File

@ -84,21 +84,16 @@ module prcfg_adc (
reg [31:0] status = 0;
reg [31:0] adc_pn_data = 0;
reg adc_dvalid_d = 0;
reg [31:0] adc_data = 0;
reg [ 7:0] adc_pn_oos_count = 0;
reg adc_pn_oos = 0;
reg adc_pn_err = 0;
reg [ 3:0] mode;
reg [ 3:0] channel_sel;
wire adc_dvalid;
wire [31:0] adc_pn_data_s;
wire adc_pn_update_s;
wire adc_pn_match_s;
wire adc_pn_oos_s;
wire adc_pn_err_s;
// prbs function
function [31:0] pn;
@ -148,34 +143,25 @@ module prcfg_adc (
mode <= control[7:4];
end
// prbs monitor
assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? src_adc_ddata : adc_pn_data;
assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
assign adc_pn_match_s = (src_adc_ddata == adc_pn_data) ? 1'b1 : 1'b0;
assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
// prbs generation
always @(posedge clk) begin
if(adc_dvalid == 1'b1) begin
adc_pn_data <= pn(adc_pn_data_s);
end
adc_dvalid_d <= adc_dvalid;
if(adc_dvalid_d == 1'b1) begin
adc_pn_err <= adc_pn_err_s;
if(adc_pn_update_s == 1'b1) begin
if(adc_pn_oos_count >= 'd16) begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= ~adc_pn_oos;
end else begin
adc_pn_oos_count <= adc_pn_oos_count + 1;
adc_pn_oos <= adc_pn_oos;
end
end else begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= adc_pn_oos;
end
end
end
assign adc_pn_data_s = (adc_pn_oos_s == 1'b1) ? src_adc_ddata : adc_pn_data;
ad_pnmon #(
.DATA_WIDTH(32)
) i_pn_mon (
.adc_clk(clk),
.adc_valid_in(adc_dvalid),
.adc_data_in(src_adc_ddata),
.adc_data_pn(adc_pn_data),
.adc_pn_oos(adc_pn_oos_s),
.adc_pn_err(adc_pn_err_s));
// rx path are passed through on test mode
always @(posedge clk) begin
dst_adc_dwr <= src_adc_dwr;
@ -183,10 +169,11 @@ module prcfg_adc (
dst_adc_ddata <= src_adc_ddata;
src_adc_dovf <= dst_adc_dovf;
end
// setup status bits for gpio_out
always @(posedge clk) begin
if((mode == 3'd2) && (channel_sel == CHANNEL_ID)) begin
status <= {22'h0, adc_pn_err, adc_pn_oos, RP_ID};
status <= {22'h0, adc_pn_err_s, adc_pn_oos_s, RP_ID};
end else begin
status <= {24'h0, RP_ID};
end

27
library/prcfg/bist/prcfg_dac.v
View File

@ -93,10 +93,7 @@ module prcfg_dac(
reg [ 3:0] mode;
wire [31:0] dac_data_mode0;
wire [31:0] dac_data_mode1;
wire [31:0] dac_data_mode2;
wire [31:0] dac_data_mode3;
wire [31:0] dac_pattern_s;
// prbs function
function [31:0] pn;
@ -144,9 +141,6 @@ module prcfg_dac(
mode <= control[7:4];
end
// pass through for tx/rx side
assign dac_data_mode0 = src_dac_ddata;
// sine tone generation
always @(posedge clk) begin
if (dst_dac_en == 1'h1) begin
@ -191,8 +185,6 @@ module prcfg_dac(
endcase
end
assign dac_data_mode1 = {cos_tone, sin_tone};
// prbs generation
always @(posedge clk) begin
if(dst_dac_en == 1'h1) begin
@ -200,8 +192,6 @@ module prcfg_dac(
end
end
assign dac_data_mode2 = dac_prbs;
// constant pattern generator
always @(posedge clk) begin
if(dst_dac_en == 1'h1) begin
@ -209,34 +199,33 @@ module prcfg_dac(
end
end
assign dac_data_mode3 = (pattern == 1'h1) ?
assign dac_pattern_s = (pattern == 1'h1) ?
{16'h5555, 16'hAAAA, 16'h5555, 16'hAAAA} :
{16'hAAAA, 16'h5555, 16'hAAAA, 16'h5555};
// output mux for tx side
always @(posedge clk) begin
src_dac_en <= (mode == 0) ? dst_dac_en : 1'b0;
dst_dac_dvalid <= (mode == 0) ? src_dac_dvalid :
((dst_dac_en == 1'b1) ? 1'b1 : 1'b0);
dst_dac_dvalid <= (mode == 0) ? src_dac_dvalid : dst_dac_en;
dst_dac_dunf <= (mode == 0) ? src_dac_dunf : 1'b0;
end
always @(posedge clk) begin
case(mode)
4'h0 : begin
dst_dac_ddata <= dac_data_mode0;
dst_dac_ddata <= src_dac_ddata;
end
4'h1 : begin
dst_dac_ddata <= dac_data_mode1;
dst_dac_ddata <= {cos_tone, sin_tone};
end
4'h2 : begin
dst_dac_ddata <= dac_data_mode2;
dst_dac_ddata <= dac_prbs;
end
4'h3 : begin
dst_dac_ddata <= dac_data_mode3;
dst_dac_ddata <= dac_pattern_s;
end
default : begin
dst_dac_ddata <= dac_data_mode0;
dst_dac_ddata <= src_dac_ddata;
end
endcase
end

4
library/prcfg/common/prcfg_top.v
View File

@ -139,7 +139,7 @@ module prcfg_top(
end else begin
prcfg_adc #(
.CHANNEL_ID(l_inst)
) i_prcfg_adc_1 (
) i_prcfg_adc_i (
.clk(clk),
.control(adc_gpio_input),
.status(adc_gpio_out_s[l_inst]),
@ -174,7 +174,7 @@ module prcfg_top(
end else begin
prcfg_dac #(
.CHANNEL_ID(l_inst)
) i_prcfg_dac_1 (
) i_prcfg_dac_i (
.clk(clk),
.control(dac_gpio_input),
.status(dac_gpio_out_s[l_inst]),

78
library/prcfg/qpsk/prcfg_adc.v
View File

@ -61,11 +61,9 @@ module prcfg_adc (
parameter CHANNEL_ID = 0;
parameter DATA_WIDTH = 32;
parameter SYMBOL_WIDTH = 2;
localparam SYMBOL_WIDTH = 2;
localparam RP_ID = 8'hA2;
localparam SYMBOLE_CNTR_WIDTH = $clog2(DATA_WIDTH/SYMBOLE_WIDTH);
localparam NROF_SYMBOLS = DATA_WIDTH/SYMBOL_WIDTH;
input clk;
@ -87,25 +85,17 @@ module prcfg_adc (
reg dst_adc_dsync = 'h0;
reg [(DATA_WIDTH-1):0] dst_adc_ddata = 'h0;
reg [(DATA_WIDTH-1):0] adc_ddata = 'h0;
reg [ 7:0] adc_pn_data = 'hF1;
reg [31:0] status = 'h0;
reg [ 3:0] mode = 'h0;
reg [ 3:0] channel_sel = 'h0;
reg [(SYMBOL_WIDTH-1):0] adc_data_buf[(NROF_SYMBOLS-1):0];
reg [(SYMBOL_CNTR_WIDTH-1):0] symbole_counter = 'h0;
reg [2:0] sample_counter = 'd0;
wire adc_dvalid;
wire dma_dvalid;
wire [(SYMBOL_WIDTH-1):0] adc_ddata_s;
wire [ 7:0] adc_pn_data_s;
wire adc_pn_err_s;
wire adc_pn_oos_s;
wire demod_en;
// prbs function
function [ 7:0] pn;
input [ 7:0] din;
@ -131,26 +121,7 @@ module prcfg_adc (
assign adc_dvalid = src_adc_dwr & src_adc_dsync;
// data concatanation (MSB first)
always @(posedge clk) begin
if(adc_dvalid == 1'b1) begin
adc_data_buf[(NROF_SYMBOLS - symbole_counter - 1)] <= adc_ddata_s;
end
end
genvar i;
generate
for (i=0; i < NROF_SYMBOLS; i = i + 1) begin: SYMBOL_WRAPPER
always @(posedge clk) begin
if((adc_dvalid == 1'b1) &&
(& symbole_counter == 1'b1) &&
(sample_counter == 'b1) &&
(mode != 0)) begin
adc_ddata[((i+1)*SYMBOL_WIDTH)-1:(i*SYMBOL_WIDTH)] <= adc_data_buf[i];
end
end
end
endgenerate
assign adc_pn_data_s = (adc_pn_oos_s == 1'b1) ? {adc_pn_data[7:2], adc_ddata_s} : adc_pn_data;
ad_pnmon #(
.DATA_WIDTH(8)
@ -158,11 +129,10 @@ module prcfg_adc (
.adc_clk(clk),
.adc_valid_in(adc_dvalid),
.adc_data_in({adc_pn_data[7:2], adc_ddata_s}),
.adc_data_pn(adc_pn_data),
.adc_data_pn(adc_pn_data_s),
.adc_pn_oos(adc_pn_oos_s),
.adc_pn_err(adc_pn_err_s));
// prbs generation
always @(posedge clk) begin
if(adc_dvalid == 1'b1) begin
@ -170,17 +140,6 @@ module prcfg_adc (
end
end
always @(posedge clk) begin
if(adc_dvalid == 1'b1) begin
if(demod_en == 1'b1) begin
symbole_counter <= symbole_counter + 1;
end
sample_counter <= sample_counter + 1;
end
end
assign demod_en = (sample_counter == 7) ? 1'b1 : 1'b0;
// qpsk demodulator
qpsk_demod i_qpsk_demod1 (
.clk(clk),
@ -193,16 +152,29 @@ module prcfg_adc (
// output logic for data ans status
always @(posedge clk) begin
src_adc_dovf <= dst_adc_dovf;
dst_adc_dsync <= src_adc_dsync;
dst_adc_dwr <= src_adc_dwr;
case(mode)
4'h0 : begin
dst_adc_ddata <= src_adc_ddata;
src_adc_dovf <= dst_adc_dovf;
end
4'h1 : begin
dst_adc_ddata <= 32'h0;
src_adc_dovf <= 1'b0;
end
4'h2 : begin
dst_adc_ddata <= {30'h0, adc_ddata_s};
src_adc_dovf <= dst_adc_dovf;
end
default : begin
dst_adc_ddata <= src_adc_ddata;
src_adc_dovf <= dst_adc_dovf;
end
endcase
if(mode == 0) begin
dst_adc_dwr <= src_adc_dwr;
dst_adc_ddata <= src_adc_ddata;
end else begin
dst_adc_ddata <= adc_ddata;
dst_adc_dwr <= (& symbole_counter) & (& sample_counter);
end
if((mode == 3'd2) && (channel_sel == CHANNEL_ID)) begin
status <= {22'h0, adc_pn_err_s, adc_pn_oos_s, RP_ID};
end else begin

74
library/prcfg/qpsk/prcfg_dac.v
View File

@ -62,11 +62,9 @@ module prcfg_dac(
parameter CHANNEL_ID = 0;
parameter DATA_WIDTH = 32;
parameter SYMBOL_WIDTH = 2;
localparam SYMBOL_WIDTH = 2;
localparam RP_ID = 8'hA2;
localparam SYMBOL_CNTR_WIDTH = $clog2(DATA_WIDTH/SYMBOL_WIDTH);
localparam NROF_SYMBOLES = DATA_WIDTH/SYMBOL_WIDTH;
input clk;
@ -94,20 +92,11 @@ module prcfg_dac(
reg [31:0] status = 'h0;
reg [ 3:0] mode = 'h0;
reg [(SYMBOL_WIDTH-1):0] dac_data_buf[(NROF_SYMBOLES-1):0];
reg [(SYMBOL_CNTR_WIDTH-1):0] symbole_counter = 'd0;
reg [2:0] sample_counter = 'd0;
// internal wires
wire [(SYMBOL_WIDTH-1):0] mod_data;
wire [15:0] dac_data_fltr_i;
wire [15:0] dac_data_fltr_q;
wire [(DATA_WIDTH-1):0] dac_data_mode0;
wire [(DATA_WIDTH-1):0] dac_data_mode1_2;
wire mod_en;
// prbs function
function [ 7:0] pn;
input [ 7:0] din;
@ -138,35 +127,8 @@ module prcfg_dac(
end
end
// symbol wrapper, data is transmitted MSB first
genvar i;
generate
for (i = 0; i < NROF_SYMBOLES; i = i + 1) begin : SYMBOLE_WRAPPER
// flop the incoming data when it's valid and all the symbols are pushed out
always @(posedge clk) begin
if((src_dac_dvalid == 1'b1) && (symbole_counter == 'd0)) begin
dac_data_buf[(NROF_SYMBOLES-i-1)] <= src_dac_ddata[((i+1)*SYMBOL_WIDTH)-1:(i*SYMBOL_WIDTH)];
end
end
end
endgenerate
// increment to counter for the symbol mux
always @(posedge clk) begin
if((src_dac_dvalid == 1'b1) && (dst_dac_en == 1'b1)) begin
if(mod_en == 1'b1) begin
symbole_counter <= symbole_counter + 1;
end
sample_counter <= sample_counter + 1;
end
end
// the modulator generate eight samples from each symbol
// to prevent data loss, need to keep each symbol at data_input port for 8 samples
assign mod_en = (sample_counter == 7) ? 1'b1 : 1'b0;
// data for the modulator (prbs or dma)
assign mod_data = (mode == 1) ? pn_data[ 1:0] : dac_data_buf[symbole_counter];
assign mod_data = (mode == 1) ? pn_data[ 1:0] : src_dac_ddata[ 1:0];
// qpsk modulator
qpsk_mod i_qpsk_mod (
@ -177,17 +139,29 @@ module prcfg_dac(
.data_qpsk_q(dac_data_fltr_q)
);
// pass through mode
assign dac_data_mode0 = src_dac_ddata;
// modulated data
assign dac_data_mode1_2 = { dac_data_fltr_q, dac_data_fltr_i };
// output logic
always @(posedge clk) begin
src_dac_en <= (& symbole_counter) & (& sample_counter);
dst_dac_dunf <= (mode == 1) ? 1'b0 : src_dac_dunf;
dst_dac_ddata <= (mode == 0) ? dac_data_mode0 : dac_data_mode1_2;
dst_dac_dvalid <= (mode == 0) ? src_dac_dvalid : ((dst_dac_en == 1'b1) ? 1'b1 : 1'b0);
end
src_dac_en <= dst_dac_en;
dst_dac_dvalid <= src_dac_dvalid;
case(mode)
4'h0 : begin
dst_dac_ddata <= src_dac_ddata;
dst_dac_dunf <= src_dac_dunf;
end
4'h1 : begin
dst_dac_ddata <= { dac_data_fltr_q, dac_data_fltr_i };
dst_dac_dunf <= 1'h0;
end
4'h2 : begin
dst_dac_ddata <= { dac_data_fltr_q, dac_data_fltr_i };
dst_dac_dunf <= src_dac_dunf;
end
default : begin
end
endcase
end
endmodule