diff --git a/library/jesd204/axi_jesd204_rx/Makefile b/library/jesd204/axi_jesd204_rx/Makefile
index ba10b7882..6a99f3472 100644
--- a/library/jesd204/axi_jesd204_rx/Makefile
+++ b/library/jesd204/axi_jesd204_rx/Makefile
@@ -12,6 +12,7 @@ GENERIC_DEPS += jesd204_up_rx.v
 GENERIC_DEPS += jesd204_up_rx_lane.v
 
 XILINX_DEPS += axi_jesd204_rx_constr.xdc
+XILINX_DEPS += axi_jesd204_rx_ooc.ttcl
 XILINX_DEPS += axi_jesd204_rx_ip.tcl
 
 XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml
diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl
index 70316b4e9..b5d33fe78 100644
--- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl
+++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl
@@ -52,11 +52,14 @@ adi_ip_files axi_jesd204_rx [list \
   "jesd204_up_rx_lane.v" \
   "jesd204_up_ilas_mem.v" \
   "axi_jesd204_rx_constr.xdc" \
+  "axi_jesd204_rx_ooc.ttcl" \
   "axi_jesd204_rx.v" \
 ]
 
 adi_ip_properties axi_jesd204_rx
 
+adi_ip_ttcl axi_jesd204_rx "axi_jesd204_rx_ooc.ttcl"
+
 set_property PROCESSING_ORDER LATE [ipx::get_files axi_jesd204_rx_constr.xdc \
   -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \
   -filter {NAME =~ *synthesis*}]]
diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl
new file mode 100644
index 000000000..e2732e424
--- /dev/null
+++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl
@@ -0,0 +1,61 @@
+#
+# The ADI JESD204 Core is released under the following license, which is
+# different than all other HDL cores in this repository.
+#
+# Please read this, and understand the freedoms and responsibilities you have
+# by using this source code/core.
+#
+# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
+#
+# This core is free software, you can use run, copy, study, change, ask
+# questions about and improve this core. Distribution of source, or resulting
+# binaries (including those inside an FPGA or ASIC) require you to release the
+# source of the entire project (excluding the system libraries provide by the
+# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
+# License version 2 as published by the Free Software Foundation.
+#
+# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License version 2
+# along with this source code, and binary.  If not, see
+# <http://www.gnu.org/licenses/>.
+#
+# Commercial licenses (with commercial support) of this JESD204 core are also
+# available under terms different than the General Public License. (e.g. they
+# do not require you to accompany any image (FPGA or ASIC) using the JESD204
+# core with any corresponding source code.) For these alternate terms you must
+# purchase a license from Analog Devices Technology Licensing Office. Users
+# interested in such a license should contact jesd204-licensing@analog.com for
+# more information. This commercial license is sub-licensable (if you purchase
+# chips from Analog Devices, incorporate them into your PCB level product, and
+# purchase a JESD204 license, end users of your product will also have a
+# license to use this core in a commercial setting without releasing their
+# source code).
+#
+# In addition, we kindly ask you to acknowledge ADI in any program, application
+# or publication in which you use this JESD204 HDL core. (You are not required
+# to do so; it is up to your common sense to decide whether you want to comply
+# with this request or not.) For general publications, we suggest referencing :
+# “The design and implementation of the JESD204 HDL Core used in this project
+# is copyright © 2016-2017, Analog Devices, Inc.”
+#
+
+<: setFileUsedIn { out_of_context synthesis implementation } :>
+<: ;#Component and file information :>
+<: set ComponentName [getComponentNameString] :>
+<: setOutputDirectory "./" :>
+<: setFileName $ComponentName :>
+<: setFileExtension "_ooc.xdc" :>
+
+# This XDC is used only for OOC mode of synthesis, implementation.
+# These are default values for timing driven synthesis during OOC flow.
+# These values will be overwritten during implementation with information
+# from top level.
+
+create_clock -name s_axi_aclk -period 10  [get_ports s_axi_aclk]
+create_clock -name core_clk   -period 2.5 [get_ports core_clk]
+
+################################################################################
+