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util_adxcvr: Expose QPLL and CPLL *_CFG attributes

main
Istvan Csomortani 2018-10-02 15:19:35 +01:00 committed by István Csomortáni
parent 740715c6b3
commit 42127c07fc
3 changed files with 141 additions and 27 deletions
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111
library/xilinx/util_adxcvr/util_adxcvr.v
View File

@ -48,11 +48,22 @@ module util_adxcvr #(
parameter integer QPLL_FBDIV_RATIO = 1,
parameter [26:0] QPLL_CFG = 27'h0680181,
parameter [ 9:0] QPLL_FBDIV = 10'b0000110000,
parameter [15:0] QPLL_CFG0 = 16'b0011001100011100,
parameter [15:0] QPLL_CFG1 = 16'b1101000000111000,
parameter [15:0] QPLL_CFG1_G3 = 16'b1101000000111000,
parameter [15:0] QPLL_CFG2 = 16'b0000111111000000,
parameter [15:0] QPLL_CFG2_G3 = 16'b0000111111000000,
parameter [15:0] QPLL_CFG3 = 16'b0000000100100000,
parameter [15:0] QPLL_CFG4 = 16'b0000000000000011,
// cpll-configuration
parameter integer CPLL_FBDIV = 2,
parameter integer CPLL_FBDIV_4_5 = 5,
parameter [15:0] CPLL_CFG0 = 16'b0000000111111010,
parameter [15:0] CPLL_CFG1 = 16'b0000000000100011,
parameter [15:0] CPLL_CFG2 = 16'b0000000000000010,
parameter [15:0] CPLL_CFG3 = 16'b0000000000000000,
// tx-configuration
@ -1063,7 +1074,14 @@ module util_adxcvr #(
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_CFG (QPLL_CFG),
.QPLL_FBDIV (QPLL_FBDIV))
.QPLL_FBDIV (QPLL_FBDIV),
.QPLL_CFG0 (QPLL_CFG0),
.QPLL_CFG1 (QPLL_CFG1),
.QPLL_CFG1_G3 (QPLL_CFG1_G3),
.QPLL_CFG2 (QPLL_CFG2),
.QPLL_CFG2_G3 (QPLL_CFG2_G3),
.QPLL_CFG3 (QPLL_CFG3),
.QPLL_CFG4 (QPLL_CFG4))
i_xcm_0 (
.qpll_ref_clk (qpll_ref_clk_0),
.qpll2ch_clk (qpll2ch_clk_0),
@ -1093,6 +1111,10 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
.TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_POLARITY ((TX_LANE_INVERT >> 0) & 1),
@ -1191,6 +1213,10 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
.TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_POLARITY ((TX_LANE_INVERT >> 1) & 1),
@ -1289,6 +1315,10 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
.TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_POLARITY ((TX_LANE_INVERT >> 2) & 1),
@ -1387,6 +1417,10 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
.TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_POLARITY ((TX_LANE_INVERT >> 3) & 1),
@ -1485,7 +1519,14 @@ module util_adxcvr #(
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_CFG (QPLL_CFG),
.QPLL_FBDIV (QPLL_FBDIV))
.QPLL_FBDIV (QPLL_FBDIV),
.QPLL_CFG0 (QPLL_CFG0),
.QPLL_CFG1 (QPLL_CFG1),
.QPLL_CFG1_G3 (QPLL_CFG1_G3),
.QPLL_CFG2 (QPLL_CFG2),
.QPLL_CFG2_G3 (QPLL_CFG2_G3),
.QPLL_CFG3 (QPLL_CFG3),
.QPLL_CFG4 (QPLL_CFG4))
i_xcm_4 (
.qpll_ref_clk (qpll_ref_clk_4),
.qpll2ch_clk (qpll2ch_clk_4),
@ -1515,6 +1556,10 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
.TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_POLARITY ((TX_LANE_INVERT >> 4) & 1),
@ -1613,6 +1658,10 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
.TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_POLARITY ((TX_LANE_INVERT >> 5) & 1),
@ -1711,6 +1760,10 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
.TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_POLARITY ((TX_LANE_INVERT >> 6) & 1),
@ -1809,6 +1862,10 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
.TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_POLARITY ((TX_LANE_INVERT >> 7) & 1),
@ -1907,7 +1964,14 @@ module util_adxcvr #(
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_CFG (QPLL_CFG),
.QPLL_FBDIV (QPLL_FBDIV))
.QPLL_FBDIV (QPLL_FBDIV),
.QPLL_CFG0 (QPLL_CFG0),
.QPLL_CFG1 (QPLL_CFG1),
.QPLL_CFG1_G3 (QPLL_CFG1_G3),
.QPLL_CFG2 (QPLL_CFG2),
.QPLL_CFG2_G3 (QPLL_CFG2_G3),
.QPLL_CFG3 (QPLL_CFG3),
.QPLL_CFG4 (QPLL_CFG4))
i_xcm_8 (
.qpll_ref_clk (qpll_ref_clk_8),
.qpll2ch_clk (qpll2ch_clk_8),
@ -1937,6 +2001,10 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
.TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_POLARITY ((TX_LANE_INVERT >> 8) & 1),
@ -2035,6 +2103,10 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
.TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_POLARITY ((TX_LANE_INVERT >> 9) & 1),
@ -2133,6 +2205,10 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
.TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_POLARITY ((TX_LANE_INVERT >> 10) & 1),
@ -2231,6 +2307,10 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
.TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_POLARITY ((TX_LANE_INVERT >> 11) & 1),
@ -2329,7 +2409,14 @@ module util_adxcvr #(
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_CFG (QPLL_CFG),
.QPLL_FBDIV (QPLL_FBDIV))
.QPLL_FBDIV (QPLL_FBDIV),
.QPLL_CFG0 (QPLL_CFG0),
.QPLL_CFG1 (QPLL_CFG1),
.QPLL_CFG1_G3 (QPLL_CFG1_G3),
.QPLL_CFG2 (QPLL_CFG2),
.QPLL_CFG2_G3 (QPLL_CFG2_G3),
.QPLL_CFG3 (QPLL_CFG3),
.QPLL_CFG4 (QPLL_CFG4))
i_xcm_12 (
.qpll_ref_clk (qpll_ref_clk_12),
.qpll2ch_clk (qpll2ch_clk_12),
@ -2359,6 +2446,10 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
.TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_POLARITY ((TX_LANE_INVERT >> 12) & 1),
@ -2457,6 +2548,10 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
.TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_POLARITY ((TX_LANE_INVERT >> 13) & 1),
@ -2555,6 +2650,10 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
.TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_POLARITY ((TX_LANE_INVERT >> 14) & 1),
@ -2653,6 +2752,10 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
.TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_POLARITY ((TX_LANE_INVERT >> 15) & 1),

20
library/xilinx/util_adxcvr/util_adxcvr_xch.v
View File

@ -43,6 +43,10 @@ module util_adxcvr_xch #(
parameter integer CPLL_FBDIV = 2,
parameter integer CPLL_FBDIV_4_5 = 5,
parameter [15:0] CPLL_CFG0 = 16'b0000000111111010,
parameter [15:0] CPLL_CFG1 = 16'b0000000000100011,
parameter [15:0] CPLL_CFG2 = 16'b0000000000000010,
parameter [15:0] CPLL_CFG3 = 16'b0000000000000000,
parameter integer TX_OUT_DIV = 1,
parameter integer TX_CLK25_DIV = 20,
@ -825,10 +829,10 @@ module util_adxcvr_xch #(
.CLK_COR_SEQ_2_ENABLE (4'b1111),
.CLK_COR_SEQ_2_USE ("FALSE"),
.CLK_COR_SEQ_LEN (1),
.CPLL_CFG0 (16'h67f8),
.CPLL_CFG1 (16'ha4ac),
.CPLL_CFG2 (16'h0007),
.CPLL_CFG3 (6'h00),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3[5:0]),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_45 (CPLL_FBDIV_4_5),
.CPLL_INIT_CFG0 (16'h02b2),
@ -1597,10 +1601,10 @@ module util_adxcvr_xch #(
.CLK_COR_SEQ_2_ENABLE (4'b1111),
.CLK_COR_SEQ_2_USE ("FALSE"),
.CLK_COR_SEQ_LEN (1),
.CPLL_CFG0 (16'b0000000111111010),
.CPLL_CFG1 (16'b0000000000100011),
.CPLL_CFG2 (16'b0000000000000010),
.CPLL_CFG3 (16'b0000000000000000),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_45 (CPLL_FBDIV_4_5),
.CPLL_INIT_CFG0 (16'b0000001010110010),

37
library/xilinx/util_adxcvr/util_adxcvr_xcm.v
View File

@ -43,7 +43,14 @@ module util_adxcvr_xcm #(
parameter integer QPLL_REFCLK_DIV = 1,
parameter integer QPLL_FBDIV_RATIO = 1,
parameter [26:0] QPLL_CFG = 27'h0680181,
parameter [ 9:0] QPLL_FBDIV = 10'b0000110000) (
parameter [ 9:0] QPLL_FBDIV = 10'b0000110000,
parameter [15:0] QPLL_CFG0 = 16'b0011001100011100,
parameter [15:0] QPLL_CFG1 = 16'b1101000000111000,
parameter [15:0] QPLL_CFG1_G3 = 16'b1101000000111000,
parameter [15:0] QPLL_CFG2 = 16'b0000111111000000,
parameter [15:0] QPLL_CFG2_G3 = 16'b0000111111000000,
parameter [15:0] QPLL_CFG3 = 16'b0000000100100000,
parameter [15:0] QPLL_CFG4 = 16'b0000000000000011) (
// reset and clocks
@ -357,13 +364,13 @@ module util_adxcvr_xcm #(
.PPF0_CFG (16'b0000011000000000),
.PPF1_CFG (16'b0000011000000000),
.QPLL0CLKOUT_RATE ("HALF"),
.QPLL0_CFG0 (16'b0011001100011100),
.QPLL0_CFG1 (16'b1101000000111000),
.QPLL0_CFG1_G3 (16'b1101000000111000),
.QPLL0_CFG2 (16'b0000111111000000),
.QPLL0_CFG2_G3 (16'b0000111111000000),
.QPLL0_CFG3 (16'b0000000100100000),
.QPLL0_CFG4 (16'b0000000000000011),
.QPLL0_CFG0 (QPLL_CFG0),
.QPLL0_CFG1 (QPLL_CFG1),
.QPLL0_CFG1_G3 (QPLL_CFG1_G3),
.QPLL0_CFG2 (QPLL_CFG2),
.QPLL0_CFG2_G3 (QPLL_CFG2_G3),
.QPLL0_CFG3 (QPLL_CFG3),
.QPLL0_CFG4 (QPLL_CFG4),
.QPLL0_CP (10'b0001111111),
.QPLL0_CP_G3 (10'b0000011111),
.QPLL0_FBDIV (QPLL_FBDIV),
@ -381,13 +388,13 @@ module util_adxcvr_xcm #(
.QPLL0_SDM_CFG1 (16'b0000000000000000),
.QPLL0_SDM_CFG2 (16'b0000000000000000),
.QPLL1CLKOUT_RATE ("HALF"),
.QPLL1_CFG0 (16'b0011001100011100),
.QPLL1_CFG1 (16'b1101000000111000),
.QPLL1_CFG1_G3 (16'b1101000000111000),
.QPLL1_CFG2 (16'b0000111111000000),
.QPLL1_CFG2_G3 (16'b0000111111000000),
.QPLL1_CFG3 (16'b0000000100100000),
.QPLL1_CFG4 (16'b0000000000000011),
.QPLL1_CFG0 (QPLL_CFG0),
.QPLL1_CFG1 (QPLL_CFG1),
.QPLL1_CFG1_G3 (QPLL_CFG1_G3),
.QPLL1_CFG2 (QPLL_CFG2),
.QPLL1_CFG2_G3 (QPLL_CFG2_G3),
.QPLL1_CFG3 (QPLL_CFG3),
.QPLL1_CFG4 (QPLL_CFG4),
.QPLL1_CP (10'b1111111111),
.QPLL1_CP_G3 (10'b0011111111),
.QPLL1_FBDIV (QPLL_FBDIV),