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Remove BASEADDR/HIGHADDR parameters 

This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2014-09-11 10:08:10 +02:00
parent 647a26e19c
commit 41cc92ef49
33 changed files with 24 additions and 144 deletions
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7
library/axi_ad9122/axi_ad9122.v
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@ -100,8 +100,6 @@ module axi_ad9122 (
parameter PCORE_DAC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_HIGHADDR = 32'hffffffff;
parameter C_BASEADDR = 32'h00000000;
// dac interface
@ -297,10 +295,7 @@ module axi_ad9122 (
// up bus interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),

4
library/axi_ad9144/axi_ad9144.v
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@ -93,8 +93,6 @@ module axi_ad9144 (
parameter PCORE_QUAD_DUAL_N = 1;
parameter PCORE_DAC_DP_DISABLE = 0;
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_HIGHADDR = 32'hffffffff;
parameter C_BASEADDR = 32'h00000000;
// jesd interface
// tx_clk is (line-rate/40)
@ -253,7 +251,7 @@ module axi_ad9144 (
// up bus interface
up_axi #(.PCORE_BASEADDR (C_BASEADDR), .PCORE_HIGHADDR (C_HIGHADDR)) i_up_axi (
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),

7
library/axi_ad9250/axi_ad9250.v
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@ -85,8 +85,6 @@ module axi_ad9250 (
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'h00000000;
parameter C_HIGHADDR = 32'hffffffff;
// jesd interface
// rx_clk is (line-rate/40)
@ -291,10 +289,7 @@ module axi_ad9250 (
// up bus interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),

4
library/axi_ad9250/axi_ad9250_alt.v
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@ -173,9 +173,7 @@ module axi_ad9250_alt (
.PCORE_ID (PCORE_ID),
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_IODELAY_GROUP ("adc_if_delay_group"),
.C_S_AXI_MIN_SIZE (32'hffff),
.C_BASEADDR (32'h00000000),
.C_HIGHADDR (32'hffffffff))
.C_S_AXI_MIN_SIZE (32'hffff))
i_ad9250 (
.rx_clk (rx_clk),
.rx_data (rx_data),

7
library/axi_ad9361/axi_ad9361.v
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@ -147,8 +147,6 @@ module axi_ad9361 (
parameter PCORE_DAC_DP_DISABLE = 0;
parameter PCORE_ADC_DP_DISABLE = 0;
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_HIGHADDR = 32'hffffffff;
parameter C_BASEADDR = 32'h00000000;
// physical interface (receive)
@ -429,10 +427,7 @@ module axi_ad9361 (
// axi interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),

4
library/axi_ad9361/axi_ad9361_alt.v
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@ -281,9 +281,7 @@ module axi_ad9361_alt (
.PCORE_ID (PCORE_ID),
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_IODELAY_GROUP ("dev_if_delay_group"),
.C_S_AXI_MIN_SIZE (32'hffff),
.C_BASEADDR (32'h00000000),
.C_HIGHADDR (32'hffffffff))
.C_S_AXI_MIN_SIZE (32'hffff))
i_ad9361 (
.rx_clk_in_p (rx_clk_in_p),
.rx_clk_in_n (rx_clk_in_n),

7
library/axi_ad9467/axi_ad9467.v
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@ -91,8 +91,6 @@ module axi_ad9467(
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_HIGHADDR = 32'hffffffff;
parameter C_BASEADDR = 32'h00000000;
// physical interface
@ -286,10 +284,7 @@ module axi_ad9467(
// up bus interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),

7
library/axi_ad9625/axi_ad9625.v
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@ -85,8 +85,6 @@ module axi_ad9625 (
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_HIGHADDR = 32'hffffffff;
parameter C_BASEADDR = 32'h00000000;
// jesd interface
// rx_clk is (line-rate/40)
@ -257,10 +255,7 @@ module axi_ad9625 (
// up bus interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),

7
library/axi_ad9643/axi_ad9643.v
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@ -97,8 +97,6 @@ module axi_ad9643 (
parameter PCORE_ADC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_HIGHADDR = 32'hffffffff;
parameter C_BASEADDR = 32'h00000000;
// adc interface (clk, data, over-range)
@ -355,10 +353,7 @@ module axi_ad9643 (
// up bus interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),

7
library/axi_ad9652/axi_ad9652.v
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@ -97,8 +97,6 @@ module axi_ad9652 (
parameter PCORE_ADC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_HIGHADDR = 32'hffffffff;
parameter C_BASEADDR = 32'h00000000;
// adc interface (clk, data, over-range)
@ -353,10 +351,7 @@ module axi_ad9652 (
// up bus interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),

7
library/axi_ad9671/axi_ad9671.v
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@ -83,8 +83,6 @@ module axi_ad9671 (
parameter PCORE_4L_2L_N = 1;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_HIGHADDR = 32'hffffffff;
parameter C_BASEADDR = 32'h00000000;
// jesd interface
// rx_clk is the jesd clock (ref_clk/2)
@ -281,10 +279,7 @@ module axi_ad9671 (
// up bus interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),

4
library/axi_ad9671/axi_ad9671_alt.v
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@ -169,9 +169,7 @@ module axi_ad9671_alt (
.PCORE_4L_2L_N (PCORE_4L_2L_N),
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_IODELAY_GROUP ("adc_if_delay_group"),
.C_S_AXI_MIN_SIZE (32'hffff),
.C_BASEADDR (32'h00000000),
.C_HIGHADDR (32'hffffffff))
.C_S_AXI_MIN_SIZE (32'hffff))
i_ad9671 (
.rx_clk (rx_clk),
.rx_data (rx_data),

7
library/axi_ad9680/axi_ad9680.v
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@ -85,8 +85,6 @@ module axi_ad9680 (
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_HIGHADDR = 32'hffffffff;
parameter C_BASEADDR = 32'h00000000;
// jesd interface
// rx_clk is (line-rate/40)
@ -291,10 +289,7 @@ module axi_ad9680 (
// up bus interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),

7
library/axi_clkgen/axi_clkgen.v
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@ -79,8 +79,6 @@ module axi_clkgen (
parameter PCORE_CLK0_DIV = 6;
parameter PCORE_CLK1_DIV = 6;
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
// clocks
@ -141,10 +139,7 @@ module axi_clkgen (
// up bus interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),

4
library/axi_dmac/axi_dmac.v
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@ -137,8 +137,6 @@ module axi_dmac (
parameter PCORE_ID = 0;
parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
parameter C_DMA_DATA_WIDTH_SRC = 64;
parameter C_DMA_DATA_WIDTH_DEST = 64;
parameter C_DMA_LENGTH_WIDTH = 24;
@ -244,8 +242,6 @@ wire [2:0] src_response_id;
wire [7:0] dbg_status;
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR)
) i_up_axi (
.up_rstn(s_axi_aresetn),
.up_clk(s_axi_aclk),

7
library/axi_hdmi_tx/axi_hdmi_tx.v
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@ -106,8 +106,6 @@ module axi_hdmi_tx (
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_EMBEDDED_SYNC = 0;
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_HIGHADDR = 32'hffffffff;
parameter C_BASEADDR = 32'h00000000;
localparam XILINX_7SERIES = 0;
localparam XILINX_ULTRASCALE = 1;
@ -234,10 +232,7 @@ module axi_hdmi_tx (
// axi interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),

4
library/axi_hdmi_tx/axi_hdmi_tx_alt.v
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@ -218,9 +218,7 @@ module axi_hdmi_tx_alt (
.PCORE_Cr_Cb_N (PCORE_Cr_Cb_N),
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_EMBEDDED_SYNC (PCORE_EMBEDDED_SYNC),
.C_S_AXI_MIN_SIZE (32'hffff),
.C_BASEADDR (32'h00000000),
.C_HIGHADDR (32'hffffffff))
.C_S_AXI_MIN_SIZE (32'hffff)
i_hdmi_tx (
.hdmi_clk (hdmi_clk),
.hdmi_out_clk (hdmi_out_clk),

2
library/axi_i2s_adi/axi_i2s_adi.vhd
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@ -29,8 +29,6 @@ entity axi_i2s_adi is
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
-- DO NOT EDIT ABOVE THIS LINE ---------------------
C_DMA_TYPE : integer := 0;

7
library/axi_jesd_gt/axi_jesd_gt.v
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@ -161,8 +161,6 @@ module axi_jesd_gt (
parameter PCORE_PMA_RSV = 32'h001E7080;
parameter PCORE_RX_CDR_CFG = 72'h0b000023ff10400020;
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'h00000000;
parameter C_HIGHADDR = 32'hffffffff;
// physical interface
@ -696,10 +694,7 @@ module axi_jesd_gt (
// axi interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),

9
library/axi_mc_controller/axi_mc_controller.v
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@ -39,9 +39,7 @@
module axi_mc_controller
#(
parameter C_S_AXI_MIN_SIZE = 32'hffff,
parameter C_BASEADDR = 32'hffffffff,
parameter C_HIGHADDR = 32'h00000000
parameter C_S_AXI_MIN_SIZE = 32'hffff
)
(
input ref_clk, // 100 MHz
@ -695,10 +693,7 @@ up_adc_common i_up_adc_common(
// up bus interface
up_axi #(
.PCORE_BASEADDR(C_BASEADDR),
.PCORE_HIGHADDR(C_HIGHADDR))
i_up_axi(
up_axi i_up_axi(
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_axi_awvalid(s_axi_awvalid),

9
library/axi_mc_current_monitor/axi_mc_current_monitor.v
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@ -39,9 +39,7 @@
module axi_mc_current_monitor
#(
parameter C_S_AXI_MIN_SIZE = 32'hffff,
parameter C_BASEADDR = 32'hffffffff,
parameter C_HIGHADDR = 32'h00000000
parameter C_S_AXI_MIN_SIZE = 32'hffff
)
(
@ -754,10 +752,7 @@ up_adc_common i_up_adc_common(
// up bus interface
up_axi #(
.PCORE_BASEADDR(C_BASEADDR),
.PCORE_HIGHADDR(C_HIGHADDR))
i_up_axi(
up_axi i_up_axi(
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_axi_awvalid(s_axi_awvalid),

7
library/axi_mc_speed/axi_mc_speed.v
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@ -40,8 +40,6 @@
module axi_mc_speed
#(
parameter C_S_AXI_MIN_SIZE = 32'hffff,
parameter C_BASEADDR = 32'hffffffff,
parameter C_HIGHADDR = 32'h00000000,
parameter MOTOR_CONTROL_REVISION = 2
)
//----------- Ports Declarations -----------------------------------------------
@ -288,10 +286,7 @@ up_adc_common i_up_adc_common(
);
// up bus interface
up_axi #(
.PCORE_BASEADDR(C_BASEADDR),
.PCORE_HIGHADDR(C_HIGHADDR))
i_up_axi(
up_axi i_up_axi(
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_axi_awvalid(s_axi_awvalid),

2
library/axi_spdif_tx/axi_spdif_tx.vhd
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@ -51,8 +51,6 @@ entity axi_spdif_tx is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_DMA_TYPE : integer := 0
);

8
library/common/up_axi.v
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@ -77,8 +77,6 @@ module up_axi (
// parameters
parameter PCORE_BASEADDR = 32'hffffffff;
parameter PCORE_HIGHADDR = 32'h00000000;
// reset and clocks
@ -147,11 +145,9 @@ module up_axi (
// wait for awvalid and wvalid before asserting awready and wready
assign up_axi_wr_s = ((up_axi_awaddr >= PCORE_BASEADDR) && (up_axi_awaddr <= PCORE_HIGHADDR)) ?
(up_axi_awvalid & up_axi_wvalid & ~up_axi_access) : 1'b0;
assign up_axi_wr_s = up_axi_awvalid & up_axi_wvalid & ~up_axi_access;
assign up_axi_rd_s = ((up_axi_araddr >= PCORE_BASEADDR) && (up_axi_araddr <= PCORE_HIGHADDR)) ?
(up_axi_arvalid & ~up_axi_access & ~up_axi_wr_s) : 1'b0;
assign up_axi_rd_s = up_axi_arvalid & ~up_axi_access & ~up_axi_wr_s;
assign up_axi_ack_s = ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) ||
((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1));

3
library/scripts/adi_ip.tcl
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@ -41,9 +41,6 @@ proc adi_ip_properties {ip_name} {
set_property vendor_display_name {Analog Devices} [ipx::current_core]
set_property company_url {www.analog.com} [ipx::current_core]
set_property value {0xFFFFFFFF} [ipx::get_hdl_parameter C_HIGHADDR [ipx::current_core]]
set_property value {0x00000000} [ipx::get_hdl_parameter C_BASEADDR [ipx::current_core]]
set_property supported_families \
{{kintexu} {Pre-Production} \
{virtexu} {Pre-Production} \

2
projects/common/ac701/ac701_system_bd.tcl
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@ -169,8 +169,6 @@ set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_
set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core
set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_spdif_tx_dma]
set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma

2
projects/common/kc705/kc705_system_bd.tcl
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@ -175,8 +175,6 @@ set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_
set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core
set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_spdif_tx_dma]
set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma

2
projects/common/kcu105/kcu105_system_bd.tcl
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@ -211,8 +211,6 @@ set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_
set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core
set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_spdif_tx_dma]
set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma

4
projects/common/mitx045/mitx045_system_bd.tcl
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@ -81,14 +81,10 @@ set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_
set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core
set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi]
set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_i2s_adi
set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_i2s_adi
set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_i2s_adi
set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_i2s_adi
# system reset/clock definitions

2
projects/common/vc707/vc707_system_bd.tcl
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@ -172,8 +172,6 @@ set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_
set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core
set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_spdif_tx_dma]
set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma

2
projects/common/zc702/zc702_system_bd.tcl
View File

@ -71,8 +71,6 @@ set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_
set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core
# system reset/clock definitions

2
projects/common/zc706/zc706_system_bd.tcl
View File

@ -71,8 +71,6 @@ set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_
set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core
# system reset/clock definitions

4
projects/common/zed/zed_system_bd.tcl
View File

@ -98,14 +98,10 @@ set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_
set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core
set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core
set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi]
set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_i2s_adi
set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_i2s_adi
set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_i2s_adi
set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_i2s_adi
# iic (fmc)