From 41cc92ef491cde14cd64338cd423d14b2ab9c4bc Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 11 Sep 2014 10:08:10 +0200 Subject: [PATCH] Remove BASEADDR/HIGHADDR parameters This is unused and unneeded. The AXI interconnect will make sure that a peripheral only gets requests that are meant for it, there is no need to check the address in the peripheral itself. Signed-off-by: Lars-Peter Clausen --- library/axi_ad9122/axi_ad9122.v | 7 +------ library/axi_ad9144/axi_ad9144.v | 4 +--- library/axi_ad9250/axi_ad9250.v | 7 +------ library/axi_ad9250/axi_ad9250_alt.v | 4 +--- library/axi_ad9361/axi_ad9361.v | 7 +------ library/axi_ad9361/axi_ad9361_alt.v | 4 +--- library/axi_ad9467/axi_ad9467.v | 7 +------ library/axi_ad9625/axi_ad9625.v | 7 +------ library/axi_ad9643/axi_ad9643.v | 7 +------ library/axi_ad9652/axi_ad9652.v | 7 +------ library/axi_ad9671/axi_ad9671.v | 7 +------ library/axi_ad9671/axi_ad9671_alt.v | 4 +--- library/axi_ad9680/axi_ad9680.v | 7 +------ library/axi_clkgen/axi_clkgen.v | 7 +------ library/axi_dmac/axi_dmac.v | 4 ---- library/axi_hdmi_tx/axi_hdmi_tx.v | 7 +------ library/axi_hdmi_tx/axi_hdmi_tx_alt.v | 4 +--- library/axi_i2s_adi/axi_i2s_adi.vhd | 2 -- library/axi_jesd_gt/axi_jesd_gt.v | 7 +------ library/axi_mc_controller/axi_mc_controller.v | 9 ++------- library/axi_mc_current_monitor/axi_mc_current_monitor.v | 9 ++------- library/axi_mc_speed/axi_mc_speed.v | 7 +------ library/axi_spdif_tx/axi_spdif_tx.vhd | 2 -- library/common/up_axi.v | 8 ++------ library/scripts/adi_ip.tcl | 3 --- projects/common/ac701/ac701_system_bd.tcl | 2 -- projects/common/kc705/kc705_system_bd.tcl | 2 -- projects/common/kcu105/kcu105_system_bd.tcl | 2 -- projects/common/mitx045/mitx045_system_bd.tcl | 4 ---- projects/common/vc707/vc707_system_bd.tcl | 2 -- projects/common/zc702/zc702_system_bd.tcl | 2 -- projects/common/zc706/zc706_system_bd.tcl | 2 -- projects/common/zed/zed_system_bd.tcl | 4 ---- 33 files changed, 24 insertions(+), 144 deletions(-) diff --git a/library/axi_ad9122/axi_ad9122.v b/library/axi_ad9122/axi_ad9122.v index e1e53b05b..0bc31dbdd 100644 --- a/library/axi_ad9122/axi_ad9122.v +++ b/library/axi_ad9122/axi_ad9122.v @@ -100,8 +100,6 @@ module axi_ad9122 ( parameter PCORE_DAC_DP_DISABLE = 0; parameter PCORE_IODELAY_GROUP = "dev_if_delay_group"; parameter C_S_AXI_MIN_SIZE = 32'hffff; - parameter C_HIGHADDR = 32'hffffffff; - parameter C_BASEADDR = 32'h00000000; // dac interface @@ -297,10 +295,7 @@ module axi_ad9122 ( // up bus interface - up_axi #( - .PCORE_BASEADDR (C_BASEADDR), - .PCORE_HIGHADDR (C_HIGHADDR)) - i_up_axi ( + up_axi i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), .up_axi_awvalid (s_axi_awvalid), diff --git a/library/axi_ad9144/axi_ad9144.v b/library/axi_ad9144/axi_ad9144.v index 48fe454c7..199a18434 100644 --- a/library/axi_ad9144/axi_ad9144.v +++ b/library/axi_ad9144/axi_ad9144.v @@ -93,8 +93,6 @@ module axi_ad9144 ( parameter PCORE_QUAD_DUAL_N = 1; parameter PCORE_DAC_DP_DISABLE = 0; parameter C_S_AXI_MIN_SIZE = 32'hffff; - parameter C_HIGHADDR = 32'hffffffff; - parameter C_BASEADDR = 32'h00000000; // jesd interface // tx_clk is (line-rate/40) @@ -253,7 +251,7 @@ module axi_ad9144 ( // up bus interface - up_axi #(.PCORE_BASEADDR (C_BASEADDR), .PCORE_HIGHADDR (C_HIGHADDR)) i_up_axi ( + up_axi i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), .up_axi_awvalid (s_axi_awvalid), diff --git a/library/axi_ad9250/axi_ad9250.v b/library/axi_ad9250/axi_ad9250.v index 7d7d04bf7..6b24324e5 100644 --- a/library/axi_ad9250/axi_ad9250.v +++ b/library/axi_ad9250/axi_ad9250.v @@ -85,8 +85,6 @@ module axi_ad9250 ( parameter PCORE_DEVICE_TYPE = 0; parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; parameter C_S_AXI_MIN_SIZE = 32'hffff; - parameter C_BASEADDR = 32'h00000000; - parameter C_HIGHADDR = 32'hffffffff; // jesd interface // rx_clk is (line-rate/40) @@ -291,10 +289,7 @@ module axi_ad9250 ( // up bus interface - up_axi #( - .PCORE_BASEADDR (C_BASEADDR), - .PCORE_HIGHADDR (C_HIGHADDR)) - i_up_axi ( + up_axi i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), .up_axi_awvalid (s_axi_awvalid), diff --git a/library/axi_ad9250/axi_ad9250_alt.v b/library/axi_ad9250/axi_ad9250_alt.v index 4e365d43a..c1f4f9802 100644 --- a/library/axi_ad9250/axi_ad9250_alt.v +++ b/library/axi_ad9250/axi_ad9250_alt.v @@ -173,9 +173,7 @@ module axi_ad9250_alt ( .PCORE_ID (PCORE_ID), .PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE), .PCORE_IODELAY_GROUP ("adc_if_delay_group"), - .C_S_AXI_MIN_SIZE (32'hffff), - .C_BASEADDR (32'h00000000), - .C_HIGHADDR (32'hffffffff)) + .C_S_AXI_MIN_SIZE (32'hffff)) i_ad9250 ( .rx_clk (rx_clk), .rx_data (rx_data), diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v index 5001b2abc..621574abe 100644 --- a/library/axi_ad9361/axi_ad9361.v +++ b/library/axi_ad9361/axi_ad9361.v @@ -147,8 +147,6 @@ module axi_ad9361 ( parameter PCORE_DAC_DP_DISABLE = 0; parameter PCORE_ADC_DP_DISABLE = 0; parameter C_S_AXI_MIN_SIZE = 32'hffff; - parameter C_HIGHADDR = 32'hffffffff; - parameter C_BASEADDR = 32'h00000000; // physical interface (receive) @@ -429,10 +427,7 @@ module axi_ad9361 ( // axi interface - up_axi #( - .PCORE_BASEADDR (C_BASEADDR), - .PCORE_HIGHADDR (C_HIGHADDR)) - i_up_axi ( + up_axi i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), .up_axi_awvalid (s_axi_awvalid), diff --git a/library/axi_ad9361/axi_ad9361_alt.v b/library/axi_ad9361/axi_ad9361_alt.v index f95553794..bf8b24e92 100644 --- a/library/axi_ad9361/axi_ad9361_alt.v +++ b/library/axi_ad9361/axi_ad9361_alt.v @@ -281,9 +281,7 @@ module axi_ad9361_alt ( .PCORE_ID (PCORE_ID), .PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE), .PCORE_IODELAY_GROUP ("dev_if_delay_group"), - .C_S_AXI_MIN_SIZE (32'hffff), - .C_BASEADDR (32'h00000000), - .C_HIGHADDR (32'hffffffff)) + .C_S_AXI_MIN_SIZE (32'hffff)) i_ad9361 ( .rx_clk_in_p (rx_clk_in_p), .rx_clk_in_n (rx_clk_in_n), diff --git a/library/axi_ad9467/axi_ad9467.v b/library/axi_ad9467/axi_ad9467.v index ea8c5d9ea..7d1f4d4e9 100644 --- a/library/axi_ad9467/axi_ad9467.v +++ b/library/axi_ad9467/axi_ad9467.v @@ -91,8 +91,6 @@ module axi_ad9467( parameter PCORE_BUFTYPE = 0; parameter PCORE_IODELAY_GROUP = "dev_if_delay_group"; parameter C_S_AXI_MIN_SIZE = 32'hffff; - parameter C_HIGHADDR = 32'hffffffff; - parameter C_BASEADDR = 32'h00000000; // physical interface @@ -286,10 +284,7 @@ module axi_ad9467( // up bus interface - up_axi #( - .PCORE_BASEADDR (C_BASEADDR), - .PCORE_HIGHADDR (C_HIGHADDR)) - i_up_axi ( + up_axi i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), .up_axi_awvalid (s_axi_awvalid), diff --git a/library/axi_ad9625/axi_ad9625.v b/library/axi_ad9625/axi_ad9625.v index 10012f0a9..5470be582 100644 --- a/library/axi_ad9625/axi_ad9625.v +++ b/library/axi_ad9625/axi_ad9625.v @@ -85,8 +85,6 @@ module axi_ad9625 ( parameter PCORE_DEVICE_TYPE = 0; parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; parameter C_S_AXI_MIN_SIZE = 32'hffff; - parameter C_HIGHADDR = 32'hffffffff; - parameter C_BASEADDR = 32'h00000000; // jesd interface // rx_clk is (line-rate/40) @@ -257,10 +255,7 @@ module axi_ad9625 ( // up bus interface - up_axi #( - .PCORE_BASEADDR (C_BASEADDR), - .PCORE_HIGHADDR (C_HIGHADDR)) - i_up_axi ( + up_axi i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), .up_axi_awvalid (s_axi_awvalid), diff --git a/library/axi_ad9643/axi_ad9643.v b/library/axi_ad9643/axi_ad9643.v index 353295d01..85fcb1e5a 100644 --- a/library/axi_ad9643/axi_ad9643.v +++ b/library/axi_ad9643/axi_ad9643.v @@ -97,8 +97,6 @@ module axi_ad9643 ( parameter PCORE_ADC_DP_DISABLE = 0; parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; parameter C_S_AXI_MIN_SIZE = 32'hffff; - parameter C_HIGHADDR = 32'hffffffff; - parameter C_BASEADDR = 32'h00000000; // adc interface (clk, data, over-range) @@ -355,10 +353,7 @@ module axi_ad9643 ( // up bus interface - up_axi #( - .PCORE_BASEADDR (C_BASEADDR), - .PCORE_HIGHADDR (C_HIGHADDR)) - i_up_axi ( + up_axi i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), .up_axi_awvalid (s_axi_awvalid), diff --git a/library/axi_ad9652/axi_ad9652.v b/library/axi_ad9652/axi_ad9652.v index 8ace7f193..1bd5c9032 100644 --- a/library/axi_ad9652/axi_ad9652.v +++ b/library/axi_ad9652/axi_ad9652.v @@ -97,8 +97,6 @@ module axi_ad9652 ( parameter PCORE_ADC_DP_DISABLE = 0; parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; parameter C_S_AXI_MIN_SIZE = 32'hffff; - parameter C_HIGHADDR = 32'hffffffff; - parameter C_BASEADDR = 32'h00000000; // adc interface (clk, data, over-range) @@ -353,10 +351,7 @@ module axi_ad9652 ( // up bus interface - up_axi #( - .PCORE_BASEADDR (C_BASEADDR), - .PCORE_HIGHADDR (C_HIGHADDR)) - i_up_axi ( + up_axi i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), .up_axi_awvalid (s_axi_awvalid), diff --git a/library/axi_ad9671/axi_ad9671.v b/library/axi_ad9671/axi_ad9671.v index 3f01ffef4..8b8c1f3f7 100644 --- a/library/axi_ad9671/axi_ad9671.v +++ b/library/axi_ad9671/axi_ad9671.v @@ -83,8 +83,6 @@ module axi_ad9671 ( parameter PCORE_4L_2L_N = 1; parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; parameter C_S_AXI_MIN_SIZE = 32'hffff; - parameter C_HIGHADDR = 32'hffffffff; - parameter C_BASEADDR = 32'h00000000; // jesd interface // rx_clk is the jesd clock (ref_clk/2) @@ -281,10 +279,7 @@ module axi_ad9671 ( // up bus interface - up_axi #( - .PCORE_BASEADDR (C_BASEADDR), - .PCORE_HIGHADDR (C_HIGHADDR)) - i_up_axi ( + up_axi i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), .up_axi_awvalid (s_axi_awvalid), diff --git a/library/axi_ad9671/axi_ad9671_alt.v b/library/axi_ad9671/axi_ad9671_alt.v index fec40c59f..87248100e 100644 --- a/library/axi_ad9671/axi_ad9671_alt.v +++ b/library/axi_ad9671/axi_ad9671_alt.v @@ -169,9 +169,7 @@ module axi_ad9671_alt ( .PCORE_4L_2L_N (PCORE_4L_2L_N), .PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE), .PCORE_IODELAY_GROUP ("adc_if_delay_group"), - .C_S_AXI_MIN_SIZE (32'hffff), - .C_BASEADDR (32'h00000000), - .C_HIGHADDR (32'hffffffff)) + .C_S_AXI_MIN_SIZE (32'hffff)) i_ad9671 ( .rx_clk (rx_clk), .rx_data (rx_data), diff --git a/library/axi_ad9680/axi_ad9680.v b/library/axi_ad9680/axi_ad9680.v index 3c3f975e7..efcf4c366 100644 --- a/library/axi_ad9680/axi_ad9680.v +++ b/library/axi_ad9680/axi_ad9680.v @@ -85,8 +85,6 @@ module axi_ad9680 ( parameter PCORE_DEVICE_TYPE = 0; parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; parameter C_S_AXI_MIN_SIZE = 32'hffff; - parameter C_HIGHADDR = 32'hffffffff; - parameter C_BASEADDR = 32'h00000000; // jesd interface // rx_clk is (line-rate/40) @@ -291,10 +289,7 @@ module axi_ad9680 ( // up bus interface - up_axi #( - .PCORE_BASEADDR (C_BASEADDR), - .PCORE_HIGHADDR (C_HIGHADDR)) - i_up_axi ( + up_axi i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), .up_axi_awvalid (s_axi_awvalid), diff --git a/library/axi_clkgen/axi_clkgen.v b/library/axi_clkgen/axi_clkgen.v index e90ecdafc..efc73b14b 100644 --- a/library/axi_clkgen/axi_clkgen.v +++ b/library/axi_clkgen/axi_clkgen.v @@ -79,8 +79,6 @@ module axi_clkgen ( parameter PCORE_CLK0_DIV = 6; parameter PCORE_CLK1_DIV = 6; parameter C_S_AXI_MIN_SIZE = 32'hffff; - parameter C_BASEADDR = 32'hffffffff; - parameter C_HIGHADDR = 32'h00000000; // clocks @@ -141,10 +139,7 @@ module axi_clkgen ( // up bus interface - up_axi #( - .PCORE_BASEADDR (C_BASEADDR), - .PCORE_HIGHADDR (C_HIGHADDR)) - i_up_axi ( + up_axi i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), .up_axi_awvalid (s_axi_awvalid), diff --git a/library/axi_dmac/axi_dmac.v b/library/axi_dmac/axi_dmac.v index 64199a56b..def990151 100644 --- a/library/axi_dmac/axi_dmac.v +++ b/library/axi_dmac/axi_dmac.v @@ -137,8 +137,6 @@ module axi_dmac ( parameter PCORE_ID = 0; -parameter C_BASEADDR = 32'hffffffff; -parameter C_HIGHADDR = 32'h00000000; parameter C_DMA_DATA_WIDTH_SRC = 64; parameter C_DMA_DATA_WIDTH_DEST = 64; parameter C_DMA_LENGTH_WIDTH = 24; @@ -244,8 +242,6 @@ wire [2:0] src_response_id; wire [7:0] dbg_status; up_axi #( - .PCORE_BASEADDR (C_BASEADDR), - .PCORE_HIGHADDR (C_HIGHADDR) ) i_up_axi ( .up_rstn(s_axi_aresetn), .up_clk(s_axi_aclk), diff --git a/library/axi_hdmi_tx/axi_hdmi_tx.v b/library/axi_hdmi_tx/axi_hdmi_tx.v index 8c74dffa0..73c9e3c03 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx.v @@ -106,8 +106,6 @@ module axi_hdmi_tx ( parameter PCORE_DEVICE_TYPE = 0; parameter PCORE_EMBEDDED_SYNC = 0; parameter C_S_AXI_MIN_SIZE = 32'hffff; - parameter C_HIGHADDR = 32'hffffffff; - parameter C_BASEADDR = 32'h00000000; localparam XILINX_7SERIES = 0; localparam XILINX_ULTRASCALE = 1; @@ -234,10 +232,7 @@ module axi_hdmi_tx ( // axi interface - up_axi #( - .PCORE_BASEADDR (C_BASEADDR), - .PCORE_HIGHADDR (C_HIGHADDR)) - i_up_axi ( + up_axi i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), .up_axi_awvalid (s_axi_awvalid), diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_alt.v b/library/axi_hdmi_tx/axi_hdmi_tx_alt.v index 9e86d2dea..d911c01fe 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_alt.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx_alt.v @@ -218,9 +218,7 @@ module axi_hdmi_tx_alt ( .PCORE_Cr_Cb_N (PCORE_Cr_Cb_N), .PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE), .PCORE_EMBEDDED_SYNC (PCORE_EMBEDDED_SYNC), - .C_S_AXI_MIN_SIZE (32'hffff), - .C_BASEADDR (32'h00000000), - .C_HIGHADDR (32'hffffffff)) + .C_S_AXI_MIN_SIZE (32'hffff) i_hdmi_tx ( .hdmi_clk (hdmi_clk), .hdmi_out_clk (hdmi_out_clk), diff --git a/library/axi_i2s_adi/axi_i2s_adi.vhd b/library/axi_i2s_adi/axi_i2s_adi.vhd index 3a46f1ddf..789420e5e 100644 --- a/library/axi_i2s_adi/axi_i2s_adi.vhd +++ b/library/axi_i2s_adi/axi_i2s_adi.vhd @@ -29,8 +29,6 @@ entity axi_i2s_adi is C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 32; C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF"; - C_BASEADDR : std_logic_vector := X"FFFFFFFF"; - C_HIGHADDR : std_logic_vector := X"00000000"; C_FAMILY : string := "virtex6"; -- DO NOT EDIT ABOVE THIS LINE --------------------- C_DMA_TYPE : integer := 0; diff --git a/library/axi_jesd_gt/axi_jesd_gt.v b/library/axi_jesd_gt/axi_jesd_gt.v index 87b3e5ee5..583eb5284 100644 --- a/library/axi_jesd_gt/axi_jesd_gt.v +++ b/library/axi_jesd_gt/axi_jesd_gt.v @@ -161,8 +161,6 @@ module axi_jesd_gt ( parameter PCORE_PMA_RSV = 32'h001E7080; parameter PCORE_RX_CDR_CFG = 72'h0b000023ff10400020; parameter C_S_AXI_MIN_SIZE = 32'hffff; - parameter C_BASEADDR = 32'h00000000; - parameter C_HIGHADDR = 32'hffffffff; // physical interface @@ -696,10 +694,7 @@ module axi_jesd_gt ( // axi interface - up_axi #( - .PCORE_BASEADDR (C_BASEADDR), - .PCORE_HIGHADDR (C_HIGHADDR)) - i_up_axi ( + up_axi i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), .up_axi_awvalid (s_axi_awvalid), diff --git a/library/axi_mc_controller/axi_mc_controller.v b/library/axi_mc_controller/axi_mc_controller.v index a0e05dd57..be3a0702d 100644 --- a/library/axi_mc_controller/axi_mc_controller.v +++ b/library/axi_mc_controller/axi_mc_controller.v @@ -39,9 +39,7 @@ module axi_mc_controller #( - parameter C_S_AXI_MIN_SIZE = 32'hffff, - parameter C_BASEADDR = 32'hffffffff, - parameter C_HIGHADDR = 32'h00000000 + parameter C_S_AXI_MIN_SIZE = 32'hffff ) ( input ref_clk, // 100 MHz @@ -695,10 +693,7 @@ up_adc_common i_up_adc_common( // up bus interface -up_axi #( - .PCORE_BASEADDR(C_BASEADDR), - .PCORE_HIGHADDR(C_HIGHADDR)) -i_up_axi( +up_axi i_up_axi( .up_rstn(up_rstn), .up_clk(up_clk), .up_axi_awvalid(s_axi_awvalid), diff --git a/library/axi_mc_current_monitor/axi_mc_current_monitor.v b/library/axi_mc_current_monitor/axi_mc_current_monitor.v index dc8fd7794..6a75c31cd 100644 --- a/library/axi_mc_current_monitor/axi_mc_current_monitor.v +++ b/library/axi_mc_current_monitor/axi_mc_current_monitor.v @@ -39,9 +39,7 @@ module axi_mc_current_monitor #( - parameter C_S_AXI_MIN_SIZE = 32'hffff, - parameter C_BASEADDR = 32'hffffffff, - parameter C_HIGHADDR = 32'h00000000 + parameter C_S_AXI_MIN_SIZE = 32'hffff ) ( @@ -754,10 +752,7 @@ up_adc_common i_up_adc_common( // up bus interface -up_axi #( - .PCORE_BASEADDR(C_BASEADDR), - .PCORE_HIGHADDR(C_HIGHADDR)) - i_up_axi( +up_axi i_up_axi( .up_rstn(up_rstn), .up_clk(up_clk), .up_axi_awvalid(s_axi_awvalid), diff --git a/library/axi_mc_speed/axi_mc_speed.v b/library/axi_mc_speed/axi_mc_speed.v index 62ccf5b1a..73be2a69b 100644 --- a/library/axi_mc_speed/axi_mc_speed.v +++ b/library/axi_mc_speed/axi_mc_speed.v @@ -40,8 +40,6 @@ module axi_mc_speed #( parameter C_S_AXI_MIN_SIZE = 32'hffff, - parameter C_BASEADDR = 32'hffffffff, - parameter C_HIGHADDR = 32'h00000000, parameter MOTOR_CONTROL_REVISION = 2 ) //----------- Ports Declarations ----------------------------------------------- @@ -288,10 +286,7 @@ up_adc_common i_up_adc_common( ); // up bus interface -up_axi #( - .PCORE_BASEADDR(C_BASEADDR), - .PCORE_HIGHADDR(C_HIGHADDR)) - i_up_axi( +up_axi i_up_axi( .up_rstn(up_rstn), .up_clk(up_clk), .up_axi_awvalid(s_axi_awvalid), diff --git a/library/axi_spdif_tx/axi_spdif_tx.vhd b/library/axi_spdif_tx/axi_spdif_tx.vhd index ac29d6f45..8c2256595 100644 --- a/library/axi_spdif_tx/axi_spdif_tx.vhd +++ b/library/axi_spdif_tx/axi_spdif_tx.vhd @@ -51,8 +51,6 @@ entity axi_spdif_tx is generic ( C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 32; - C_BASEADDR : std_logic_vector := X"FFFFFFFF"; - C_HIGHADDR : std_logic_vector := X"00000000"; C_FAMILY : string := "virtex6"; C_DMA_TYPE : integer := 0 ); diff --git a/library/common/up_axi.v b/library/common/up_axi.v index 513f58e4d..8fdda891b 100644 --- a/library/common/up_axi.v +++ b/library/common/up_axi.v @@ -77,8 +77,6 @@ module up_axi ( // parameters - parameter PCORE_BASEADDR = 32'hffffffff; - parameter PCORE_HIGHADDR = 32'h00000000; // reset and clocks @@ -147,11 +145,9 @@ module up_axi ( // wait for awvalid and wvalid before asserting awready and wready - assign up_axi_wr_s = ((up_axi_awaddr >= PCORE_BASEADDR) && (up_axi_awaddr <= PCORE_HIGHADDR)) ? - (up_axi_awvalid & up_axi_wvalid & ~up_axi_access) : 1'b0; + assign up_axi_wr_s = up_axi_awvalid & up_axi_wvalid & ~up_axi_access; - assign up_axi_rd_s = ((up_axi_araddr >= PCORE_BASEADDR) && (up_axi_araddr <= PCORE_HIGHADDR)) ? - (up_axi_arvalid & ~up_axi_access & ~up_axi_wr_s) : 1'b0; + assign up_axi_rd_s = up_axi_arvalid & ~up_axi_access & ~up_axi_wr_s; assign up_axi_ack_s = ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) || ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)); diff --git a/library/scripts/adi_ip.tcl b/library/scripts/adi_ip.tcl index 2381c4f1f..da3c453ca 100644 --- a/library/scripts/adi_ip.tcl +++ b/library/scripts/adi_ip.tcl @@ -41,9 +41,6 @@ proc adi_ip_properties {ip_name} { set_property vendor_display_name {Analog Devices} [ipx::current_core] set_property company_url {www.analog.com} [ipx::current_core] - set_property value {0xFFFFFFFF} [ipx::get_hdl_parameter C_HIGHADDR [ipx::current_core]] - set_property value {0x00000000} [ipx::get_hdl_parameter C_BASEADDR [ipx::current_core]] - set_property supported_families \ {{kintexu} {Pre-Production} \ {virtexu} {Pre-Production} \ diff --git a/projects/common/ac701/ac701_system_bd.tcl b/projects/common/ac701/ac701_system_bd.tcl index d3ebd5c8d..16644e26a 100755 --- a/projects/common/ac701/ac701_system_bd.tcl +++ b/projects/common/ac701/ac701_system_bd.tcl @@ -169,8 +169,6 @@ set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_ set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_spdif_tx_dma] set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl index 026fee2ec..79cea6a1b 100644 --- a/projects/common/kc705/kc705_system_bd.tcl +++ b/projects/common/kc705/kc705_system_bd.tcl @@ -175,8 +175,6 @@ set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_ set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_spdif_tx_dma] set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl index 1c1a3c25a..78cfae4b2 100644 --- a/projects/common/kcu105/kcu105_system_bd.tcl +++ b/projects/common/kcu105/kcu105_system_bd.tcl @@ -211,8 +211,6 @@ set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_ set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_spdif_tx_dma] set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma diff --git a/projects/common/mitx045/mitx045_system_bd.tcl b/projects/common/mitx045/mitx045_system_bd.tcl index 7bbd00071..fe39a5403 100755 --- a/projects/common/mitx045/mitx045_system_bd.tcl +++ b/projects/common/mitx045/mitx045_system_bd.tcl @@ -81,14 +81,10 @@ set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_ set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi] set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_i2s_adi set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_i2s_adi -set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_i2s_adi -set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_i2s_adi # system reset/clock definitions diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl index 6b9ff8705..541b6996c 100644 --- a/projects/common/vc707/vc707_system_bd.tcl +++ b/projects/common/vc707/vc707_system_bd.tcl @@ -172,8 +172,6 @@ set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_ set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_spdif_tx_dma] set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma diff --git a/projects/common/zc702/zc702_system_bd.tcl b/projects/common/zc702/zc702_system_bd.tcl index 1e90e57f0..b2ec711d3 100644 --- a/projects/common/zc702/zc702_system_bd.tcl +++ b/projects/common/zc702/zc702_system_bd.tcl @@ -71,8 +71,6 @@ set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_ set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core # system reset/clock definitions diff --git a/projects/common/zc706/zc706_system_bd.tcl b/projects/common/zc706/zc706_system_bd.tcl index b57d8e8fb..319e87998 100644 --- a/projects/common/zc706/zc706_system_bd.tcl +++ b/projects/common/zc706/zc706_system_bd.tcl @@ -71,8 +71,6 @@ set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_ set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core # system reset/clock definitions diff --git a/projects/common/zed/zed_system_bd.tcl b/projects/common/zed/zed_system_bd.tcl index a3f1dc325..21932d6be 100644 --- a/projects/common/zed/zed_system_bd.tcl +++ b/projects/common/zed/zed_system_bd.tcl @@ -98,14 +98,10 @@ set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_ set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi] set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_i2s_adi set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_i2s_adi -set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_i2s_adi -set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_i2s_adi # iic (fmc)