axi_adrv9001/axi_adrv9001_core.v: Disable TDD and IOCTRL if second SSI interface is disabled
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dfe153dc68
commit
41525f348b
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@ -563,6 +563,7 @@ module axi_ad9001_core #(
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up_delay_cntrl #(
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.DATA_WIDTH(NUM_LANES),
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.DRP_WIDTH(DRP_WIDTH),
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.DISABLE(DISABLE_RX2_SSI),
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.BASE_ADDRESS(6'h06))
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i_delay_cntrl_rx2 (
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.delay_clk (delay_clk),
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@ -582,15 +583,13 @@ module axi_ad9001_core #(
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.up_rdata (up_rdata_s[5]),
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.up_rack (up_rack_s[5]));
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generate
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if (TDD_DISABLE == 0) begin
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wire tdd_rx2_rf_en_loc;
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wire tdd_tx2_rf_en_loc;
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wire tdd_if2_mode_loc;
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axi_adrv9001_tdd #(
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.BASE_ADDRESS (6'h12)
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.BASE_ADDRESS (6'h12),
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.ENABLED (TDD_DISABLE==0)
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) i_tdd_1 (
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.clk (rx1_clk),
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.rst (rx1_rst),
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@ -616,7 +615,8 @@ module axi_ad9001_core #(
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.up_rack (up_rack_s[6]));
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axi_adrv9001_tdd #(
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.BASE_ADDRESS (6'h13)
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.BASE_ADDRESS (6'h13),
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.ENABLED(TDD_DISABLE == 0 && (DISABLE_RX2_SSI == 0 || DISABLE_TX2_SSI == 0))
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) i_tdd_2 (
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.clk (rx2_clk),
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.rst (rx2_rst_loc),
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@ -647,25 +647,5 @@ module axi_ad9001_core #(
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assign tdd_sync_cntr = tdd_sync_cntr1 | tdd_sync_cntr2;
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end else begin
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assign up_wack_s[6] = 1'b0;
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assign up_rack_s[6] = 1'b0;
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assign up_rdata_s[6] = 32'h0;
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assign up_wack_s[7] = 1'b0;
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assign up_rack_s[7] = 1'b0;
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assign up_rdata_s[7] = 32'h0;
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assign tdd_rx1_rf_en = 1'b1;
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assign tdd_tx1_rf_en = 1'b1;
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assign tdd_if1_mode = 1'b0;
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assign tdd_tx1_valid = 1'b1;
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assign tdd_rx1_valid = 1'b1;
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assign tdd_rx2_rf_en = 1'b1;
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assign tdd_tx2_rf_en = 1'b1;
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assign tdd_if2_mode = 1'b0;
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assign tdd_tx2_valid = 1'b1;
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assign tdd_rx2_valid = 1'b1;
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end
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endgenerate
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endmodule
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