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ad9081_fmca_ebz: Fix device clocks termination 

The device clocks are AC coupled LVDS lines without external termination.
For proper operation internal differential termination must be enabled,
the DQS_BIAS will DC bias the AC coupled signal to VCCO/2 (1.8/2) 0.9V
main
Laszlo Nagy 2020-10-05 08:49:00 +01:00 committed by Laszlo Nagy
parent 1c208c01d6
commit 4026eaa19b
2 changed files with 169 additions and 169 deletions
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8
projects/ad9081_fmca_ebz/vcu118/system_constr.xdc
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@ -10,8 +10,8 @@ set_property -dict {PACKAGE_PIN N32 IOSTANDARD LVCMOS18
set_property -dict {PACKAGE_PIN M32 IOSTANDARD LVCMOS18 } [get_ports agc2[1] ] ; ## IO_L23N_T3U_N9_45
set_property -dict {PACKAGE_PIN M35 IOSTANDARD LVCMOS18 } [get_ports agc3[0] ] ; ## IO_L24P_T3U_N10_45
set_property -dict {PACKAGE_PIN L35 IOSTANDARD LVCMOS18 } [get_ports agc3[1] ] ; ## IO_L24N_T3U_N11_45
set_property -dict {PACKAGE_PIN P36 IOSTANDARD LVDS } [get_ports clkin6_n ] ; ## IO_L14N_T2L_N3_GC_45
set_property -dict {PACKAGE_PIN P35 IOSTANDARD LVDS } [get_ports clkin6_p ] ; ## IO_L14P_T2L_N2_GC_45
set_property -dict {PACKAGE_PIN P36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin6_n ] ; ## IO_L14N_T2L_N3_GC_45
set_property -dict {PACKAGE_PIN P35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin6_p ] ; ## IO_L14P_T2L_N2_GC_45
set_property -dict {PACKAGE_PIN AM39 } [get_ports clkin8_n ] ; ## MGTREFCLK1N_120
set_property -dict {PACKAGE_PIN AM38 } [get_ports clkin8_p ] ; ## MGTREFCLK1P_120
set_property -dict {PACKAGE_PIN AK39 } [get_ports fpga_refclk_in_n ] ; ## MGTREFCLK0N_121
@ -83,8 +83,8 @@ set_property -dict {PACKAGE_PIN AT37 IOSTANDARD LVCMOS18
set_property -dict {PACKAGE_PIN AH33 IOSTANDARD LVCMOS18 } [get_ports spi1_csb ] ; ## IO_L21P_T3L_N4_AD8P_43
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS18 } [get_ports spi1_sclk ] ; ## IO_L17P_T2U_N8_AD10P_43
set_property -dict {PACKAGE_PIN AH34 IOSTANDARD LVCMOS18 } [get_ports spi1_sdio ] ; ## IO_L21N_T3L_N5_AD8N_43
set_property -dict {PACKAGE_PIN AM32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref2_n ] ; ## IO_L13N_T2L_N1_GC_QBC_43
set_property -dict {PACKAGE_PIN AL32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref2_p ] ; ## IO_L13P_T2L_N0_GC_QBC_43
set_property -dict {PACKAGE_PIN AM32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports sysref2_n ] ; ## IO_L13N_T2L_N1_GC_QBC_43
set_property -dict {PACKAGE_PIN AL32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports sysref2_p ] ; ## IO_L13P_T2L_N0_GC_QBC_43
set_property -dict {PACKAGE_PIN AJ33 IOSTANDARD LVCMOS18 } [get_ports txen[0] ] ; ## IO_L19P_T3L_N0_DBC_AD9P_43
set_property -dict {PACKAGE_PIN AK33 IOSTANDARD LVCMOS18 } [get_ports txen[1] ] ; ## IO_L19N_T3L_N1_DBC_AD9N_43

12
projects/ad9081_fmca_ebz/zcu102/system_constr.xdc
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@ -10,10 +10,10 @@ set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18
set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS18 } [get_ports agc2[1] ] ; ## FMC0_LA20_N IO_L22N_T3U_N7_DBC_AD0N_67
set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS18 } [get_ports agc3[0] ] ; ## FMC0_LA21_P IO_L21P_T3L_N4_AD8P_67
set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18 } [get_ports agc3[1] ] ; ## FMC0_LA21_N IO_L21N_T3L_N5_AD8N_67
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS } [get_ports clkin10_n ] ; ## FMC0_CLK2_IO_N IO_L13N_T2L_N1_GC_QBC_66
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS } [get_ports clkin10_p ] ; ## FMC0_CLK2_IO_P IO_L13P_T2L_N0_GC_QBC_66
set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVDS } [get_ports clkin6_n ] ; ## FMC0_CLK1_M2C_N IO_L12N_T1U_N11_GC_67
set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVDS } [get_ports clkin6_p ] ; ## FMC0_CLK1_M2C_P IO_L12P_T1U_N10_GC_67
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin10_n ] ; ## FMC0_CLK2_IO_N IO_L13N_T2L_N1_GC_QBC_66
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin10_p ] ; ## FMC0_CLK2_IO_P IO_L13P_T2L_N0_GC_QBC_66
set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin6_n ] ; ## FMC0_CLK1_M2C_N IO_L12N_T1U_N11_GC_67
set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin6_p ] ; ## FMC0_CLK1_M2C_P IO_L12P_T1U_N10_GC_67
set_property -dict {PACKAGE_PIN G7 } [get_ports fpga_refclk_in_n ] ; ## FMC0_GBTCLK0_M2C_N MGTREFCLK0N_229
set_property -dict {PACKAGE_PIN G8 } [get_ports fpga_refclk_in_p ] ; ## FMC0_GBTCLK0_M2C_P MGTREFCLK0P_229
set_property -quiet -dict {PACKAGE_PIN F1 } [get_ports rx_data_n[2] ] ; ## FMC0_DP2_M2C_N MGTHRXN3_229 FPGA_SERDIN_0_N
@ -81,8 +81,8 @@ set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS18
set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18 } [get_ports spi1_csb ] ; ## FMC0_LA12_P IO_L9P_T1L_N4_AD12P_66
set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18 } [get_ports spi1_sclk ] ; ## FMC0_LA11_P IO_L10P_T1U_N6_QBC_AD4P_66
set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18 } [get_ports spi1_sdio ] ; ## FMC0_LA12_N IO_L9N_T1L_N5_AD12N_66
set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref2_n ] ; ## FMC0_CLK0_M2C_N IO_L12N_T1U_N11_GC_66
set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref2_p ] ; ## FMC0_CLK0_M2C_P IO_L12P_T1U_N10_GC_66
set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports sysref2_n ] ; ## FMC0_CLK0_M2C_N IO_L12N_T1U_N11_GC_66
set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports sysref2_p ] ; ## FMC0_CLK0_M2C_P IO_L12P_T1U_N10_GC_66
set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS18 } [get_ports txen[0] ] ; ## FMC0_LA09_P IO_L24P_T3U_N10_66
set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS18 } [get_ports txen[1] ] ; ## FMC0_LA09_N IO_L24N_T3U_N11_66