From 3fa9a30f0ed5f6a71834af2530d359181babdfe9 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 6 Mar 2017 14:12:25 -0500 Subject: [PATCH] a10soc/plddr4- lower mem clk to meet timing --- projects/adrv9371x/a10soc/system_constr.sdc | 2 +- projects/common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/projects/adrv9371x/a10soc/system_constr.sdc b/projects/adrv9371x/a10soc/system_constr.sdc index d7ab191fd..24cf41281 100644 --- a/projects/adrv9371x/a10soc/system_constr.sdc +++ b/projects/adrv9371x/a10soc/system_constr.sdc @@ -5,7 +5,7 @@ create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk} create_clock -period "8.139 ns" -name ref_clk0_122mhz [get_ports {ref_clk0}] create_clock -period "8.139 ns" -name ref_clk1_122mhz [get_ports {ref_clk1}] create_clock -period "7.503 ns" -name hps_ddr_ref_clk_133mhz [get_ports {hps_ddr_ref_clk}] -create_clock -period "7.503 ns" -name sys_ddr_ref_clk_133mhz [get_ports {sys_ddr_ref_clk}] +create_clock -period "10.000 ns" -name sys_ddr_ref_clk_100mhz [get_ports {sys_ddr_ref_clk}] derive_pll_clocks derive_clock_uncertainty diff --git a/projects/common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl b/projects/common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl index 2b0c56064..cfff7a279 100644 --- a/projects/common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl +++ b/projects/common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl @@ -3,9 +3,9 @@ add_instance sys_ddr4_cntrl altera_emif 16.0 set_instance_parameter_value sys_ddr4_cntrl {PROTOCOL_ENUM} {PROTOCOL_DDR4} -set_instance_parameter_value sys_ddr4_cntrl {PHY_DDR4_MEM_CLK_FREQ_MHZ} {1066.667} +set_instance_parameter_value sys_ddr4_cntrl {PHY_DDR4_MEM_CLK_FREQ_MHZ} {800.0} set_instance_parameter_value sys_ddr4_cntrl {PHY_DDR4_DEFAULT_REF_CLK_FREQ} {0} -set_instance_parameter_value sys_ddr4_cntrl {PHY_DDR4_USER_REF_CLK_FREQ_MHZ} {133.333} +set_instance_parameter_value sys_ddr4_cntrl {PHY_DDR4_USER_REF_CLK_FREQ_MHZ} {100.0} set_instance_parameter_value sys_ddr4_cntrl {PHY_DDR4_RATE_ENUM} {RATE_QUARTER} set_instance_parameter_value sys_ddr4_cntrl {MEM_DDR4_FORMAT_ENUM} {MEM_FORMAT_UDIMM} set_instance_parameter_value sys_ddr4_cntrl {MEM_DDR4_DQ_WIDTH} {64}