diff --git a/library/axi_jesd_gt/axi_jesd_gt.v b/library/axi_jesd_gt/axi_jesd_gt.v index 2000f79ee..6f6bc8f1a 100644 --- a/library/axi_jesd_gt/axi_jesd_gt.v +++ b/library/axi_jesd_gt/axi_jesd_gt.v @@ -37,926 +37,1203 @@ `timescale 1ns/100ps -module axi_jesd_gt ( +module axi_jesd_gt #( - // physical interface + parameter integer ID = 0, + parameter integer GTH_GTX_N = 0, + parameter integer QPLL0_MSEL = 0, + parameter integer QPLL0_ENABLE = 1, + parameter integer QPLL0_REFCLK_DIV = 1, + parameter [26:0] QPLL0_CFG = 27'h0680181, + parameter integer QPLL0_FBDIV_RATIO = 1'b1, + parameter [ 9:0] QPLL0_FBDIV = 10'b0000110000, + parameter integer QPLL1_MSEL = 0, + parameter integer QPLL1_ENABLE = 1, + parameter integer QPLL1_REFCLK_DIV = 1, + parameter [26:0] QPLL1_CFG = 27'h0680181, + parameter integer QPLL1_FBDIV_RATIO = 1'b1, + parameter [ 9:0] QPLL1_FBDIV = 10'b0000110000, - ref_clk_q, - ref_clk_c, + parameter [31:0] PMA_RSV_0 = 32'h001E7080, + parameter integer CPLL_FBDIV_0 = 2, + parameter integer PLL_MSEL_0 = 0, + parameter [31:0] PMA_RSV_1 = 32'h001E7080, + parameter integer CPLL_FBDIV_1 = 2, + parameter integer PLL_MSEL_1 = 1, + parameter [31:0] PMA_RSV_2 = 32'h001E7080, + parameter integer CPLL_FBDIV_2 = 2, + parameter integer PLL_MSEL_2 = 2, + parameter [31:0] PMA_RSV_3 = 32'h001E7080, + parameter integer CPLL_FBDIV_3 = 2, + parameter integer PLL_MSEL_3 = 3, + parameter [31:0] PMA_RSV_4 = 32'h001E7080, + parameter integer CPLL_FBDIV_4 = 2, + parameter integer PLL_MSEL_4 = 4, + parameter [31:0] PMA_RSV_5 = 32'h001E7080, + parameter integer CPLL_FBDIV_5 = 2, + parameter integer PLL_MSEL_5 = 5, + parameter [31:0] PMA_RSV_6 = 32'h001E7080, + parameter integer CPLL_FBDIV_6 = 2, + parameter integer PLL_MSEL_6 = 6, + parameter [31:0] PMA_RSV_7 = 32'h001E7080, + parameter integer CPLL_FBDIV_7 = 2, + parameter integer PLL_MSEL_7 = 7, - rx_data_p, - rx_data_n, - rx_sync, - rx_sysref, - rx_ext_sysref, + parameter integer RX_NUM_OF_LANES = 8, + parameter integer RX_OUT_DIV_0 = 1, + parameter integer RX_CLK25_DIV_0 = 20, + parameter integer RX_CLKBUF_ENABLE_0 = 1, + parameter integer RX_PRIMARY_0 = 0, + parameter [71:0] RX_CDR_CFG_0 = 72'h0b000023ff10400020, + parameter integer RX_MSEL_0 = 0, + parameter integer RX_OUT_DIV_1 = 1, + parameter integer RX_CLK25_DIV_1 = 20, + parameter integer RX_CLKBUF_ENABLE_1 = 1, + parameter integer RX_PRIMARY_1 = 1, + parameter [71:0] RX_CDR_CFG_1 = 72'h0b000023ff10400020, + parameter integer RX_MSEL_1 = 1, + parameter integer RX_OUT_DIV_2 = 1, + parameter integer RX_CLK25_DIV_2 = 20, + parameter integer RX_CLKBUF_ENABLE_2 = 1, + parameter integer RX_PRIMARY_2 = 2, + parameter [71:0] RX_CDR_CFG_2 = 72'h0b000023ff10400020, + parameter integer RX_MSEL_2 = 2, + parameter integer RX_OUT_DIV_3 = 1, + parameter integer RX_CLK25_DIV_3 = 20, + parameter integer RX_CLKBUF_ENABLE_3 = 1, + parameter integer RX_PRIMARY_3 = 3, + parameter [71:0] RX_CDR_CFG_3 = 72'h0b000023ff10400020, + parameter integer RX_MSEL_3 = 3, + parameter integer RX_OUT_DIV_4 = 1, + parameter integer RX_CLK25_DIV_4 = 20, + parameter integer RX_CLKBUF_ENABLE_4 = 1, + parameter integer RX_PRIMARY_4 = 4, + parameter [71:0] RX_CDR_CFG_4 = 72'h0b000023ff10400020, + parameter integer RX_MSEL_4 = 4, + parameter integer RX_OUT_DIV_5 = 1, + parameter integer RX_CLK25_DIV_5 = 20, + parameter integer RX_CLKBUF_ENABLE_5 = 1, + parameter integer RX_PRIMARY_5 = 5, + parameter [71:0] RX_CDR_CFG_5 = 72'h0b000023ff10400020, + parameter integer RX_MSEL_5 = 5, + parameter integer RX_OUT_DIV_6 = 1, + parameter integer RX_CLK25_DIV_6 = 20, + parameter integer RX_CLKBUF_ENABLE_6 = 1, + parameter integer RX_PRIMARY_6 = 6, + parameter [71:0] RX_CDR_CFG_6 = 72'h0b000023ff10400020, + parameter integer RX_MSEL_6 = 6, + parameter integer RX_OUT_DIV_7 = 1, + parameter integer RX_CLK25_DIV_7 = 20, + parameter integer RX_CLKBUF_ENABLE_7 = 1, + parameter integer RX_PRIMARY_7 = 7, + parameter [71:0] RX_CDR_CFG_7 = 72'h0b000023ff10400020, + parameter integer RX_MSEL_7 = 7, - tx_data_p, - tx_data_n, - tx_sync, - tx_sysref, - tx_ext_sysref, + parameter integer TX_NUM_OF_LANES = 8, + parameter integer TX_OUT_DIV_0 = 1, + parameter integer TX_CLK25_DIV_0 = 20, + parameter integer TX_CLKBUF_ENABLE_0 = 1, + parameter integer TX_PRIMARY_0 = 0, + parameter integer TX_DATA_SEL_0 = 0, + parameter integer TX_MSEL_0 = 0, + parameter integer TX_OUT_DIV_1 = 1, + parameter integer TX_CLK25_DIV_1 = 20, + parameter integer TX_CLKBUF_ENABLE_1 = 1, + parameter integer TX_PRIMARY_1 = 1, + parameter integer TX_DATA_SEL_1 = 1, + parameter integer TX_MSEL_1 = 1, + parameter integer TX_OUT_DIV_2 = 1, + parameter integer TX_CLK25_DIV_2 = 20, + parameter integer TX_CLKBUF_ENABLE_2 = 1, + parameter integer TX_PRIMARY_2 = 2, + parameter integer TX_DATA_SEL_2 = 2, + parameter integer TX_MSEL_2 = 2, + parameter integer TX_OUT_DIV_3 = 1, + parameter integer TX_CLK25_DIV_3 = 20, + parameter integer TX_CLKBUF_ENABLE_3 = 1, + parameter integer TX_PRIMARY_3 = 3, + parameter integer TX_DATA_SEL_3 = 3, + parameter integer TX_MSEL_3 = 3, + parameter integer TX_OUT_DIV_4 = 1, + parameter integer TX_CLK25_DIV_4 = 20, + parameter integer TX_CLKBUF_ENABLE_4 = 1, + parameter integer TX_PRIMARY_4 = 4, + parameter integer TX_DATA_SEL_4 = 4, + parameter integer TX_MSEL_4 = 4, + parameter integer TX_OUT_DIV_5 = 1, + parameter integer TX_CLK25_DIV_5 = 20, + parameter integer TX_CLKBUF_ENABLE_5 = 1, + parameter integer TX_PRIMARY_5 = 5, + parameter integer TX_DATA_SEL_5 = 5, + parameter integer TX_MSEL_5 = 5, + parameter integer TX_OUT_DIV_6 = 1, + parameter integer TX_CLK25_DIV_6 = 20, + parameter integer TX_CLKBUF_ENABLE_6 = 1, + parameter integer TX_PRIMARY_6 = 6, + parameter integer TX_DATA_SEL_6 = 6, + parameter integer TX_MSEL_6 = 6, + parameter integer TX_OUT_DIV_7 = 1, + parameter integer TX_CLK25_DIV_7 = 20, + parameter integer TX_CLKBUF_ENABLE_7 = 1, + parameter integer TX_PRIMARY_7 = 7, + parameter integer TX_DATA_SEL_7 = 7, + parameter integer TX_MSEL_7 = 7) - // core interface + ( - rx_rst, - rx_jesd_rst, - rx_clk_g, - rx_clk, - rx_data, - rx_sof, - rx_rst_done, - rx_ip_comma_align, - rx_ip_sync, - rx_ip_sof, - rx_ip_data, - rx_gt_charisk_0, - rx_gt_disperr_0, - rx_gt_notintable_0, - rx_gt_data_0, - rx_gt_charisk_1, - rx_gt_disperr_1, - rx_gt_notintable_1, - rx_gt_data_1, - rx_gt_charisk_2, - rx_gt_disperr_2, - rx_gt_notintable_2, - rx_gt_data_2, - rx_gt_charisk_3, - rx_gt_disperr_3, - rx_gt_notintable_3, - rx_gt_data_3, - rx_gt_charisk_4, - rx_gt_disperr_4, - rx_gt_notintable_4, - rx_gt_data_4, - rx_gt_charisk_5, - rx_gt_disperr_5, - rx_gt_notintable_5, - rx_gt_data_5, - rx_gt_charisk_6, - rx_gt_disperr_6, - rx_gt_notintable_6, - rx_gt_data_6, - rx_gt_charisk_7, - rx_gt_disperr_7, - rx_gt_notintable_7, - rx_gt_data_7, + // pll clocks - rx_gt_ilas_f_0, - rx_gt_ilas_q_0, - rx_gt_ilas_a_0, - rx_gt_ilas_r_0, - rx_gt_cgs_k_0, - rx_gt_ilas_f_1, - rx_gt_ilas_q_1, - rx_gt_ilas_a_1, - rx_gt_ilas_r_1, - rx_gt_cgs_k_1, - rx_gt_ilas_f_2, - rx_gt_ilas_q_2, - rx_gt_ilas_a_2, - rx_gt_ilas_r_2, - rx_gt_cgs_k_2, - rx_gt_ilas_f_3, - rx_gt_ilas_q_3, - rx_gt_ilas_a_3, - rx_gt_ilas_r_3, - rx_gt_cgs_k_3, - rx_gt_ilas_f_4, - rx_gt_ilas_q_4, - rx_gt_ilas_a_4, - rx_gt_ilas_r_4, - rx_gt_cgs_k_4, - rx_gt_ilas_f_5, - rx_gt_ilas_q_5, - rx_gt_ilas_a_5, - rx_gt_ilas_r_5, - rx_gt_cgs_k_5, - rx_gt_ilas_f_6, - rx_gt_ilas_q_6, - rx_gt_ilas_a_6, - rx_gt_ilas_r_6, - rx_gt_cgs_k_6, - rx_gt_ilas_f_7, - rx_gt_ilas_q_7, - rx_gt_ilas_a_7, - rx_gt_ilas_r_7, - rx_gt_cgs_k_7, + input qpll0_ref_clk_in, + input qpll1_ref_clk_in, + input cpll_ref_clk_in, - tx_rst, - tx_jesd_rst, - tx_clk_g, - tx_clk, - tx_data, - tx_rst_done, - tx_ip_sync, - tx_ip_sof, - tx_ip_data, - tx_gt_charisk_0, - tx_gt_data_0, - tx_gt_charisk_1, - tx_gt_data_1, - tx_gt_charisk_2, - tx_gt_data_2, - tx_gt_charisk_3, - tx_gt_data_3, - tx_gt_charisk_4, - tx_gt_data_4, - tx_gt_charisk_5, - tx_gt_data_5, - tx_gt_charisk_6, - tx_gt_data_6, - tx_gt_charisk_7, - tx_gt_data_7, + // channel interface (rx) + + input [(( 1*RX_NUM_OF_LANES)-1):0] rx_p, + input [(( 1*RX_NUM_OF_LANES)-1):0] rx_n, + + output rx_out_clk_0, + input rx_clk_0, + output rx_rst_0, + input rx_sysref_0, + output rx_sync_0, + output rx_sof_0, + output [31:0] rx_data_0, + output [ 3:0] rx_gt_charisk_0, + output [ 3:0] rx_gt_disperr_0, + output [ 3:0] rx_gt_notintable_0, + output [31:0] rx_gt_data_0, + input rx_gt_comma_align_enb_0, + output [ 3:0] rx_gt_ilas_f_0, + output [ 3:0] rx_gt_ilas_q_0, + output [ 3:0] rx_gt_ilas_a_0, + output [ 3:0] rx_gt_ilas_r_0, + output [ 3:0] rx_gt_cgs_k_0, + output rx_ip_rst_0, + input [ 3:0] rx_ip_sof_0, + input [31:0] rx_ip_data_0, + output rx_ip_sysref_0, + input rx_ip_sync_0, + output rx_ip_rst_done_0, + + output rx_out_clk_1, + input rx_clk_1, + output rx_rst_1, + input rx_sysref_1, + output rx_sync_1, + output rx_sof_1, + output [31:0] rx_data_1, + output [ 3:0] rx_gt_charisk_1, + output [ 3:0] rx_gt_disperr_1, + output [ 3:0] rx_gt_notintable_1, + output [31:0] rx_gt_data_1, + input rx_gt_comma_align_enb_1, + output [ 3:0] rx_gt_ilas_f_1, + output [ 3:0] rx_gt_ilas_q_1, + output [ 3:0] rx_gt_ilas_a_1, + output [ 3:0] rx_gt_ilas_r_1, + output [ 3:0] rx_gt_cgs_k_1, + output rx_ip_rst_1, + input [ 3:0] rx_ip_sof_1, + input [31:0] rx_ip_data_1, + output rx_ip_sysref_1, + input rx_ip_sync_1, + output rx_ip_rst_done_1, + + output rx_out_clk_2, + input rx_clk_2, + output rx_rst_2, + input rx_sysref_2, + output rx_sync_2, + output rx_sof_2, + output [31:0] rx_data_2, + output [ 3:0] rx_gt_charisk_2, + output [ 3:0] rx_gt_disperr_2, + output [ 3:0] rx_gt_notintable_2, + output [31:0] rx_gt_data_2, + input rx_gt_comma_align_enb_2, + output [ 3:0] rx_gt_ilas_f_2, + output [ 3:0] rx_gt_ilas_q_2, + output [ 3:0] rx_gt_ilas_a_2, + output [ 3:0] rx_gt_ilas_r_2, + output [ 3:0] rx_gt_cgs_k_2, + output rx_ip_rst_2, + input [ 3:0] rx_ip_sof_2, + input [31:0] rx_ip_data_2, + output rx_ip_sysref_2, + input rx_ip_sync_2, + output rx_ip_rst_done_2, + + output rx_out_clk_3, + input rx_clk_3, + output rx_rst_3, + input rx_sysref_3, + output rx_sync_3, + output rx_sof_3, + output [31:0] rx_data_3, + output [ 3:0] rx_gt_charisk_3, + output [ 3:0] rx_gt_disperr_3, + output [ 3:0] rx_gt_notintable_3, + output [31:0] rx_gt_data_3, + input rx_gt_comma_align_enb_3, + output [ 3:0] rx_gt_ilas_f_3, + output [ 3:0] rx_gt_ilas_q_3, + output [ 3:0] rx_gt_ilas_a_3, + output [ 3:0] rx_gt_ilas_r_3, + output [ 3:0] rx_gt_cgs_k_3, + output rx_ip_rst_3, + input [ 3:0] rx_ip_sof_3, + input [31:0] rx_ip_data_3, + output rx_ip_sysref_3, + input rx_ip_sync_3, + output rx_ip_rst_done_3, + + output rx_out_clk_4, + input rx_clk_4, + output rx_rst_4, + input rx_sysref_4, + output rx_sync_4, + output rx_sof_4, + output [31:0] rx_data_4, + output [ 3:0] rx_gt_charisk_4, + output [ 3:0] rx_gt_disperr_4, + output [ 3:0] rx_gt_notintable_4, + output [31:0] rx_gt_data_4, + input rx_gt_comma_align_enb_4, + output [ 3:0] rx_gt_ilas_f_4, + output [ 3:0] rx_gt_ilas_q_4, + output [ 3:0] rx_gt_ilas_a_4, + output [ 3:0] rx_gt_ilas_r_4, + output [ 3:0] rx_gt_cgs_k_4, + output rx_ip_rst_4, + input [ 3:0] rx_ip_sof_4, + input [31:0] rx_ip_data_4, + output rx_ip_sysref_4, + input rx_ip_sync_4, + output rx_ip_rst_done_4, + + output rx_out_clk_5, + input rx_clk_5, + output rx_rst_5, + input rx_sysref_5, + output rx_sync_5, + output rx_sof_5, + output [31:0] rx_data_5, + output [ 3:0] rx_gt_charisk_5, + output [ 3:0] rx_gt_disperr_5, + output [ 3:0] rx_gt_notintable_5, + output [31:0] rx_gt_data_5, + input rx_gt_comma_align_enb_5, + output [ 3:0] rx_gt_ilas_f_5, + output [ 3:0] rx_gt_ilas_q_5, + output [ 3:0] rx_gt_ilas_a_5, + output [ 3:0] rx_gt_ilas_r_5, + output [ 3:0] rx_gt_cgs_k_5, + output rx_ip_rst_5, + input [ 3:0] rx_ip_sof_5, + input [31:0] rx_ip_data_5, + output rx_ip_sysref_5, + input rx_ip_sync_5, + output rx_ip_rst_done_5, + + output rx_out_clk_6, + input rx_clk_6, + output rx_rst_6, + input rx_sysref_6, + output rx_sync_6, + output rx_sof_6, + output [31:0] rx_data_6, + output [ 3:0] rx_gt_charisk_6, + output [ 3:0] rx_gt_disperr_6, + output [ 3:0] rx_gt_notintable_6, + output [31:0] rx_gt_data_6, + input rx_gt_comma_align_enb_6, + output [ 3:0] rx_gt_ilas_f_6, + output [ 3:0] rx_gt_ilas_q_6, + output [ 3:0] rx_gt_ilas_a_6, + output [ 3:0] rx_gt_ilas_r_6, + output [ 3:0] rx_gt_cgs_k_6, + output rx_ip_rst_6, + input [ 3:0] rx_ip_sof_6, + input [31:0] rx_ip_data_6, + output rx_ip_sysref_6, + input rx_ip_sync_6, + output rx_ip_rst_done_6, + + output rx_out_clk_7, + input rx_clk_7, + output rx_rst_7, + input rx_sysref_7, + output rx_sync_7, + output rx_sof_7, + output [31:0] rx_data_7, + output [ 3:0] rx_gt_charisk_7, + output [ 3:0] rx_gt_disperr_7, + output [ 3:0] rx_gt_notintable_7, + output [31:0] rx_gt_data_7, + input rx_gt_comma_align_enb_7, + output [ 3:0] rx_gt_ilas_f_7, + output [ 3:0] rx_gt_ilas_q_7, + output [ 3:0] rx_gt_ilas_a_7, + output [ 3:0] rx_gt_ilas_r_7, + output [ 3:0] rx_gt_cgs_k_7, + output rx_ip_rst_7, + input [ 3:0] rx_ip_sof_7, + input [31:0] rx_ip_data_7, + output rx_ip_sysref_7, + input rx_ip_sync_7, + output rx_ip_rst_done_7, + + // channel interface (tx) + + output [(( 1*TX_NUM_OF_LANES)-1):0] tx_p, + output [(( 1*TX_NUM_OF_LANES)-1):0] tx_n, + + output tx_out_clk_0, + input tx_clk_0, + output tx_rst_0, + input tx_sysref_0, + input tx_sync_0, + input [31:0] tx_data_0, + input [ 3:0] tx_gt_charisk_0, + input [31:0] tx_gt_data_0, + output tx_ip_rst_0, + output [31:0] tx_ip_data_0, + output tx_ip_sysref_0, + output tx_ip_sync_0, + output tx_ip_rst_done_0, + + output tx_out_clk_1, + input tx_clk_1, + output tx_rst_1, + input tx_sysref_1, + input tx_sync_1, + input [31:0] tx_data_1, + input [ 3:0] tx_gt_charisk_1, + input [31:0] tx_gt_data_1, + output tx_ip_rst_1, + output [31:0] tx_ip_data_1, + output tx_ip_sysref_1, + output tx_ip_sync_1, + output tx_ip_rst_done_1, + + output tx_out_clk_2, + input tx_clk_2, + output tx_rst_2, + input tx_sysref_2, + input tx_sync_2, + input [31:0] tx_data_2, + input [ 3:0] tx_gt_charisk_2, + input [31:0] tx_gt_data_2, + output tx_ip_rst_2, + output [31:0] tx_ip_data_2, + output tx_ip_sysref_2, + output tx_ip_sync_2, + output tx_ip_rst_done_2, + + output tx_out_clk_3, + input tx_clk_3, + output tx_rst_3, + input tx_sysref_3, + input tx_sync_3, + input [31:0] tx_data_3, + input [ 3:0] tx_gt_charisk_3, + input [31:0] tx_gt_data_3, + output tx_ip_rst_3, + output [31:0] tx_ip_data_3, + output tx_ip_sysref_3, + output tx_ip_sync_3, + output tx_ip_rst_done_3, + + output tx_out_clk_4, + input tx_clk_4, + output tx_rst_4, + input tx_sysref_4, + input tx_sync_4, + input [31:0] tx_data_4, + input [ 3:0] tx_gt_charisk_4, + input [31:0] tx_gt_data_4, + output tx_ip_rst_4, + output [31:0] tx_ip_data_4, + output tx_ip_sysref_4, + output tx_ip_sync_4, + output tx_ip_rst_done_4, + + output tx_out_clk_5, + input tx_clk_5, + output tx_rst_5, + input tx_sysref_5, + input tx_sync_5, + input [31:0] tx_data_5, + input [ 3:0] tx_gt_charisk_5, + input [31:0] tx_gt_data_5, + output tx_ip_rst_5, + output [31:0] tx_ip_data_5, + output tx_ip_sysref_5, + output tx_ip_sync_5, + output tx_ip_rst_done_5, + + output tx_out_clk_6, + input tx_clk_6, + output tx_rst_6, + input tx_sysref_6, + input tx_sync_6, + input [31:0] tx_data_6, + input [ 3:0] tx_gt_charisk_6, + input [31:0] tx_gt_data_6, + output tx_ip_rst_6, + output [31:0] tx_ip_data_6, + output tx_ip_sysref_6, + output tx_ip_sync_6, + output tx_ip_rst_done_6, + + output tx_out_clk_7, + input tx_clk_7, + output tx_rst_7, + input tx_sysref_7, + input tx_sync_7, + input [31:0] tx_data_7, + input [ 3:0] tx_gt_charisk_7, + input [31:0] tx_gt_data_7, + output tx_ip_rst_7, + output [31:0] tx_ip_data_7, + output tx_ip_sysref_7, + output tx_ip_sync_7, + output tx_ip_rst_done_7, // axi - clock & reset - axi_aclk, - axi_aresetn, - - // axi-lite (slave) - - s_axi_awvalid, - s_axi_awaddr, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arready, - s_axi_rvalid, - s_axi_rdata, - s_axi_rresp, - s_axi_rready, - - // axi (master) - - m_axi_awvalid, - m_axi_awaddr, - m_axi_awprot, - m_axi_awready, - m_axi_wvalid, - m_axi_wdata, - m_axi_wstrb, - m_axi_wready, - m_axi_bvalid, - m_axi_bresp, - m_axi_bready, - m_axi_arvalid, - m_axi_araddr, - m_axi_arprot, - m_axi_arready, - m_axi_rvalid, - m_axi_rdata, - m_axi_rresp, - m_axi_rready); - - parameter PCORE_ID = 0; - parameter PCORE_DEVICE_TYPE = 0; - parameter PCORE_NUM_OF_TX_LANES = 4; - parameter PCORE_NUM_OF_RX_LANES = 4; - parameter PCORE_QPLL_REFCLK_DIV = 1; - parameter PCORE_QPLL_CFG = 27'h0680181; - parameter PCORE_QPLL_FBDIV_RATIO = 1'b1; - parameter PCORE_QPLL_FBDIV = 10'b0000110000; - parameter PCORE_CPLL_FBDIV = 2; - parameter PCORE_RX_OUT_DIV = 1; - parameter PCORE_TX_OUT_DIV = 1; - parameter PCORE_RX_CLK25_DIV = 20; - parameter PCORE_TX_CLK25_DIV = 20; - parameter PCORE_PMA_RSV = 32'h001E7080; - parameter PCORE_RX_CDR_CFG = 72'h0b000023ff10400020; - parameter PCORE_TX_LANE_SEL_0 = 0; - parameter PCORE_TX_LANE_SEL_1 = 1; - parameter PCORE_TX_LANE_SEL_2 = 2; - parameter PCORE_TX_LANE_SEL_3 = 3; - parameter PCORE_TX_LANE_SEL_4 = 4; - parameter PCORE_TX_LANE_SEL_5 = 5; - parameter PCORE_TX_LANE_SEL_6 = 6; - parameter PCORE_TX_LANE_SEL_7 = 7; - parameter PCORE_TX_LANE_SEL_8 = 8; - - localparam PCORE_NUM_OF_LANES = (PCORE_NUM_OF_TX_LANES > PCORE_NUM_OF_RX_LANES) ? - PCORE_NUM_OF_TX_LANES : PCORE_NUM_OF_RX_LANES; - - // physical interface - - input ref_clk_q; - input ref_clk_c; - - input [((PCORE_NUM_OF_RX_LANES* 1)-1):0] rx_data_p; - input [((PCORE_NUM_OF_RX_LANES* 1)-1):0] rx_data_n; - output rx_sync; - output rx_sysref; - input rx_ext_sysref; - - output [((PCORE_NUM_OF_TX_LANES* 1)-1):0] tx_data_p; - output [((PCORE_NUM_OF_TX_LANES* 1)-1):0] tx_data_n; - input tx_sync; - output tx_sysref; - input tx_ext_sysref; - - // core interface - - output rx_rst; - output rx_jesd_rst; - output rx_clk_g; - input rx_clk; - output [((PCORE_NUM_OF_RX_LANES*32)-1):0] rx_data; - output [((PCORE_NUM_OF_RX_LANES* 1)-1):0] rx_sof; - output rx_rst_done; - input rx_ip_comma_align; - input rx_ip_sync; - input [ 3:0] rx_ip_sof; - input [((PCORE_NUM_OF_RX_LANES*32)-1):0] rx_ip_data; - output [ 3:0] rx_gt_charisk_0; - output [ 3:0] rx_gt_disperr_0; - output [ 3:0] rx_gt_notintable_0; - output [ 31:0] rx_gt_data_0; - output [ 3:0] rx_gt_charisk_1; - output [ 3:0] rx_gt_disperr_1; - output [ 3:0] rx_gt_notintable_1; - output [ 31:0] rx_gt_data_1; - output [ 3:0] rx_gt_charisk_2; - output [ 3:0] rx_gt_disperr_2; - output [ 3:0] rx_gt_notintable_2; - output [ 31:0] rx_gt_data_2; - output [ 3:0] rx_gt_charisk_3; - output [ 3:0] rx_gt_disperr_3; - output [ 3:0] rx_gt_notintable_3; - output [ 31:0] rx_gt_data_3; - output [ 3:0] rx_gt_charisk_4; - output [ 3:0] rx_gt_disperr_4; - output [ 3:0] rx_gt_notintable_4; - output [ 31:0] rx_gt_data_4; - output [ 3:0] rx_gt_charisk_5; - output [ 3:0] rx_gt_disperr_5; - output [ 3:0] rx_gt_notintable_5; - output [ 31:0] rx_gt_data_5; - output [ 3:0] rx_gt_charisk_6; - output [ 3:0] rx_gt_disperr_6; - output [ 3:0] rx_gt_notintable_6; - output [ 31:0] rx_gt_data_6; - output [ 3:0] rx_gt_charisk_7; - output [ 3:0] rx_gt_disperr_7; - output [ 3:0] rx_gt_notintable_7; - output [ 31:0] rx_gt_data_7; - - output [ 3:0] rx_gt_ilas_f_0; - output [ 3:0] rx_gt_ilas_q_0; - output [ 3:0] rx_gt_ilas_a_0; - output [ 3:0] rx_gt_ilas_r_0; - output [ 3:0] rx_gt_cgs_k_0; - output [ 3:0] rx_gt_ilas_f_1; - output [ 3:0] rx_gt_ilas_q_1; - output [ 3:0] rx_gt_ilas_a_1; - output [ 3:0] rx_gt_ilas_r_1; - output [ 3:0] rx_gt_cgs_k_1; - output [ 3:0] rx_gt_ilas_f_2; - output [ 3:0] rx_gt_ilas_q_2; - output [ 3:0] rx_gt_ilas_a_2; - output [ 3:0] rx_gt_ilas_r_2; - output [ 3:0] rx_gt_cgs_k_2; - output [ 3:0] rx_gt_ilas_f_3; - output [ 3:0] rx_gt_ilas_q_3; - output [ 3:0] rx_gt_ilas_a_3; - output [ 3:0] rx_gt_ilas_r_3; - output [ 3:0] rx_gt_cgs_k_3; - output [ 3:0] rx_gt_ilas_f_4; - output [ 3:0] rx_gt_ilas_q_4; - output [ 3:0] rx_gt_ilas_a_4; - output [ 3:0] rx_gt_ilas_r_4; - output [ 3:0] rx_gt_cgs_k_4; - output [ 3:0] rx_gt_ilas_f_5; - output [ 3:0] rx_gt_ilas_q_5; - output [ 3:0] rx_gt_ilas_a_5; - output [ 3:0] rx_gt_ilas_r_5; - output [ 3:0] rx_gt_cgs_k_5; - output [ 3:0] rx_gt_ilas_f_6; - output [ 3:0] rx_gt_ilas_q_6; - output [ 3:0] rx_gt_ilas_a_6; - output [ 3:0] rx_gt_ilas_r_6; - output [ 3:0] rx_gt_cgs_k_6; - output [ 3:0] rx_gt_ilas_f_7; - output [ 3:0] rx_gt_ilas_q_7; - output [ 3:0] rx_gt_ilas_a_7; - output [ 3:0] rx_gt_ilas_r_7; - output [ 3:0] rx_gt_cgs_k_7; - - output tx_rst; - output tx_jesd_rst; - output tx_clk_g; - input tx_clk; - input [((PCORE_NUM_OF_TX_LANES*32)-1):0] tx_data; - output tx_rst_done; - output tx_ip_sync; - input [ 3:0] tx_ip_sof; - output [((PCORE_NUM_OF_TX_LANES*32)-1):0] tx_ip_data; - input [ 3:0] tx_gt_charisk_0; - input [ 31:0] tx_gt_data_0; - input [ 3:0] tx_gt_charisk_1; - input [ 31:0] tx_gt_data_1; - input [ 3:0] tx_gt_charisk_2; - input [ 31:0] tx_gt_data_2; - input [ 3:0] tx_gt_charisk_3; - input [ 31:0] tx_gt_data_3; - input [ 3:0] tx_gt_charisk_4; - input [ 31:0] tx_gt_data_4; - input [ 3:0] tx_gt_charisk_5; - input [ 31:0] tx_gt_data_5; - input [ 3:0] tx_gt_charisk_6; - input [ 31:0] tx_gt_data_6; - input [ 3:0] tx_gt_charisk_7; - input [ 31:0] tx_gt_data_7; - - input axi_aclk; - input axi_aresetn; + input axi_aclk, + input axi_aresetn, // axi interface - input s_axi_awvalid; - input [ 31:0] s_axi_awaddr; - output s_axi_awready; - input s_axi_wvalid; - input [ 31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [ 31:0] s_axi_araddr; - output s_axi_arready; - output s_axi_rvalid; - output [ 31:0] s_axi_rdata; - output [ 1:0] s_axi_rresp; - input s_axi_rready; + input s_axi_awvalid, + input [ 31:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [ 31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [ 31:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready, // master interface - output m_axi_awvalid; - output [ 31:0] m_axi_awaddr; - output [ 2:0] m_axi_awprot; - input m_axi_awready; - output m_axi_wvalid; - output [ 31:0] m_axi_wdata; - output [ 3:0] m_axi_wstrb; - input m_axi_wready; - input m_axi_bvalid; - input [ 1:0] m_axi_bresp; - output m_axi_bready; - output m_axi_arvalid; - output [ 31:0] m_axi_araddr; - output [ 2:0] m_axi_arprot; - input m_axi_arready; - input m_axi_rvalid; - input [ 31:0] m_axi_rdata; - input [ 1:0] m_axi_rresp; - output m_axi_rready; + output m_axi_awvalid, + output [ 31:0] m_axi_awaddr, + output [ 2:0] m_axi_awprot, + input m_axi_awready, + output m_axi_wvalid, + output [ 31:0] m_axi_wdata, + output [ 3:0] m_axi_wstrb, + input m_axi_wready, + input m_axi_bvalid, + input [ 1:0] m_axi_bresp, + output m_axi_bready, + output m_axi_arvalid, + output [ 31:0] m_axi_araddr, + output [ 2:0] m_axi_arprot, + input m_axi_arready, + input m_axi_rvalid, + input [ 31:0] m_axi_rdata, + input [ 1:0] m_axi_rresp, + output m_axi_rready); - // reset and clocks + // post-processing + + localparam integer NUM_OF_LANES = (TX_NUM_OF_LANES > RX_NUM_OF_LANES) ? + TX_NUM_OF_LANES : RX_NUM_OF_LANES; + localparam [31:0] PMA_RSV[7:0] = {PMA_RSV_7, PMA_RSV_6, PMA_RSV_5, PMA_RSV_4, + PMA_RSV_3, PMA_RSV_2, PMA_RSV_1, PMA_RSV_0}; + localparam integer CPLL_FBDIV[7:0] = {CPLL_FBDIV_7, CPLL_FBDIV_6, CPLL_FBDIV_5, CPLL_FBDIV_4, + CPLL_FBDIV_3, CPLL_FBDIV_2, CPLL_FBDIV_1, CPLL_FBDIV_0}; + localparam integer PLL_MSEL[7:0] = {PLL_MSEL_7, PLL_MSEL_6, PLL_MSEL_5, PLL_MSEL_4, + PLL_MSEL_3, PLL_MSEL_2, PLL_MSEL_1, PLL_MSEL_0}; - wire gt_pll_rst; - wire gt_rx_rst; - wire gt_tx_rst; - wire qpll_clk_0; - wire qpll_ref_clk_0; - wire qpll_clk_1; - wire qpll_ref_clk_1; - wire [ 7:0] qpll_clk; - wire [ 7:0] qpll_ref_clk; - wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_out_clk; - wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_out_clk; - wire up_rstn; - wire up_clk; - wire up_drp_rst; + localparam integer RX_OUT_DIV[7:0] = {RX_OUT_DIV_7, RX_OUT_DIV_6, RX_OUT_DIV_5, + RX_OUT_DIV_4, RX_OUT_DIV_3, RX_OUT_DIV_2, RX_OUT_DIV_1, RX_OUT_DIV_0}; + localparam integer RX_CLK25_DIV[7:0] = {RX_CLK25_DIV_7, RX_CLK25_DIV_6, RX_CLK25_DIV_5, + RX_CLK25_DIV_4, RX_CLK25_DIV_3, RX_CLK25_DIV_2, RX_CLK25_DIV_1, RX_CLK25_DIV_0}; + localparam integer RX_CLKBUF_ENABLE[7:0] = {RX_CLKBUF_ENABLE_7, RX_CLKBUF_ENABLE_6, + RX_CLKBUF_ENABLE_5, RX_CLKBUF_ENABLE_4, RX_CLKBUF_ENABLE_3, + RX_CLKBUF_ENABLE_2, RX_CLKBUF_ENABLE_1, RX_CLKBUF_ENABLE_0}; + localparam integer RX_PRIMARY[7:0] = {RX_PRIMARY_7, RX_PRIMARY_6, RX_PRIMARY_5, + RX_PRIMARY_4, RX_PRIMARY_3, RX_PRIMARY_2, RX_PRIMARY_1, RX_PRIMARY_0}; + localparam [71:0] RX_CDR_CFG[7:0] = {RX_CDR_CFG_7, RX_CDR_CFG_6, RX_CDR_CFG_5, + RX_CDR_CFG_4, RX_CDR_CFG_3, RX_CDR_CFG_2, RX_CDR_CFG_1, RX_CDR_CFG_0}; + localparam integer RX_MSEL[7:0] = {RX_MSEL_7, RX_MSEL_6, RX_MSEL_5, RX_MSEL_4, + RX_MSEL_3, RX_MSEL_2, RX_MSEL_1, RX_MSEL_0}; - // per gt interface- max -8 + localparam integer TX_OUT_DIV[7:0] = {TX_OUT_DIV_7, TX_OUT_DIV_6, TX_OUT_DIV_5, + TX_OUT_DIV_4, TX_OUT_DIV_3, TX_OUT_DIV_2, TX_OUT_DIV_1, TX_OUT_DIV_0}; + localparam integer TX_CLK25_DIV[7:0] = {TX_CLK25_DIV_7, TX_CLK25_DIV_6, TX_CLK25_DIV_5, + TX_CLK25_DIV_4, TX_CLK25_DIV_3, TX_CLK25_DIV_2, TX_CLK25_DIV_1, TX_CLK25_DIV_0}; + localparam integer TX_CLKBUF_ENABLE[7:0] = {TX_CLKBUF_ENABLE_7, TX_CLKBUF_ENABLE_6, + TX_CLKBUF_ENABLE_5, TX_CLKBUF_ENABLE_4, TX_CLKBUF_ENABLE_3, + TX_CLKBUF_ENABLE_2, TX_CLKBUF_ENABLE_1, TX_CLKBUF_ENABLE_0}; + localparam integer TX_PRIMARY[7:0] = {TX_PRIMARY_7, TX_PRIMARY_6, TX_PRIMARY_5, + TX_PRIMARY_4, TX_PRIMARY_3, TX_PRIMARY_2, TX_PRIMARY_1, TX_PRIMARY_0}; + localparam integer TX_DATA_SEL[7:0] = {TX_DATA_SEL_7, TX_DATA_SEL_6, TX_DATA_SEL_5, + TX_DATA_SEL_4, TX_DATA_SEL_3, TX_DATA_SEL_2, TX_DATA_SEL_1, TX_DATA_SEL_0}; + localparam integer TX_MSEL[7:0] = {TX_MSEL_7, TX_MSEL_6, TX_MSEL_5, TX_MSEL_4, + TX_MSEL_3, TX_MSEL_2, TX_MSEL_1, TX_MSEL_0}; - wire [((8* 4)-1):0] rx_gt_charisk; - wire [((8* 4)-1):0] rx_gt_disperr; - wire [((8* 4)-1):0] rx_gt_notintable; - wire [((8*32)-1):0] rx_gt_data; - wire [((8* 4)-1):0] rx_gt_ilas_f; - wire [((8* 4)-1):0] rx_gt_ilas_q; - wire [((8* 4)-1):0] rx_gt_ilas_a; - wire [((8* 4)-1):0] rx_gt_ilas_r; - wire [((8* 4)-1):0] rx_gt_cgs_k; - wire [((8* 4)-1):0] tx_gt_charisk; - wire [((8*32)-1):0] tx_gt_data; + // internal registers + + reg up_wack_d = 'd0; + reg up_rack_d = 'd0; + reg [ 31:0] up_rdata_d = 'd0; // internal signals - wire [ 8:0] up_status_extn_s; - wire [ 8:0] rx_rst_done_extn_s; - wire [ 8:0] rx_pll_locked_extn_s; - wire [ 8:0] tx_rst_done_extn_s; - wire [ 8:0] tx_pll_locked_extn_s; - wire [ 15:0] up_drp_rdata_gt_s[15:0]; - wire up_drp_ready_gt_s[15:0]; - wire [ 7:0] up_drp_rxrate_gt_s[15:0]; - wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_data_p_s; - wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_data_n_s; - wire [((PCORE_NUM_OF_LANES*32)-1):0] rx_data_s; - wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_sof_s; - wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_charisk_s; - wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_disperr_s; - wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_notintable_s; - wire [((PCORE_NUM_OF_LANES*32)-1):0] rx_gt_data_s; - wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_ilas_f_s; - wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_ilas_q_s; - wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_ilas_a_s; - wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_ilas_r_s; - wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_cgs_k_s; - wire [((PCORE_NUM_OF_LANES*32)-1):0] rx_ip_data_s; - wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_data_p_s; - wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_data_n_s; - wire [((PCORE_NUM_OF_LANES* 4)-1):0] tx_gt_charisk_s; - wire [((PCORE_NUM_OF_LANES*32)-1):0] tx_gt_data_s; - wire [287:0] tx_gt_data_extn_zero_s; - wire [ 35:0] tx_gt_charisk_extn_zero_s; - wire [287:0] tx_gt_data_extn_s; - wire [ 35:0] tx_gt_charisk_extn_s; - wire [287:0] tx_gt_data_mux_s; - wire [ 35:0] tx_gt_charisk_mux_s; - wire qpll_locked_0_s; - wire qpll_locked_1_s; - wire [ 7:0] qpll_locked_s; - wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_rst_done_s; - wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_pll_locked_s; - wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_rst_done_s; - wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_pll_locked_s; - wire up_lpm_dfe_n_s; - wire up_cpll_pd_s; - wire [ 1:0] up_rx_sys_clk_sel_s; - wire [ 2:0] up_rx_out_clk_sel_s; - wire [ 1:0] up_tx_sys_clk_sel_s; - wire [ 2:0] up_tx_out_clk_sel_s; - wire up_drp_sel_s; - wire up_drp_wr_s; - wire [ 11:0] up_drp_addr_s; - wire [ 15:0] up_drp_wdata_s; - wire [ 15:0] up_drp_rdata_s; - wire up_drp_ready_s; - wire [ 7:0] up_drp_lanesel_s; - wire [ 7:0] up_drp_rxrate_s; - wire up_es_drp_sel_s; - wire up_es_drp_wr_s; - wire [ 11:0] up_es_drp_addr_s; - wire [ 15:0] up_es_drp_wdata_s; - wire [ 15:0] up_es_drp_rdata_s; - wire up_es_drp_ready_s; - wire up_es_start_s; - wire up_es_stop_s; - wire up_es_init_s; - wire up_es_lpm_dfe_n_s; - wire [ 15:0] up_es_sdata0_s; - wire [ 15:0] up_es_sdata1_s; - wire [ 15:0] up_es_sdata2_s; - wire [ 15:0] up_es_sdata3_s; - wire [ 15:0] up_es_sdata4_s; - wire [ 15:0] up_es_qdata0_s; - wire [ 15:0] up_es_qdata1_s; - wire [ 15:0] up_es_qdata2_s; - wire [ 15:0] up_es_qdata3_s; - wire [ 15:0] up_es_qdata4_s; - wire [ 4:0] up_es_prescale_s; - wire [ 11:0] up_es_hoffset_min_s; - wire [ 11:0] up_es_hoffset_max_s; - wire [ 11:0] up_es_hoffset_step_s; - wire [ 7:0] up_es_voffset_min_s; - wire [ 7:0] up_es_voffset_max_s; - wire [ 7:0] up_es_voffset_step_s; - wire [ 1:0] up_es_voffset_range_s; - wire [ 31:0] up_es_start_addr_s; - wire up_es_dmaerr_s; - wire up_es_status_s; - wire up_wreq_s; - wire [ 13:0] up_waddr_s; - wire [ 31:0] up_wdata_s; - wire up_wack_s; - wire up_rreq_s; - wire [ 13:0] up_raddr_s; - wire [ 31:0] up_rdata_s; - wire up_rack_s; - - // bad tools -- bad interfaces - - assign rx_gt_charisk_0 = rx_gt_charisk[((1* 4)-1):(0* 4)]; - assign rx_gt_disperr_0 = rx_gt_disperr[((1* 4)-1):(0* 4)]; - assign rx_gt_notintable_0 = rx_gt_notintable[((1* 4)-1):(0* 4)]; - assign rx_gt_data_0 = rx_gt_data[((1*32)-1):(0*32)]; - assign rx_gt_charisk_1 = rx_gt_charisk[((2* 4)-1):(1* 4)]; - assign rx_gt_disperr_1 = rx_gt_disperr[((2* 4)-1):(1* 4)]; - assign rx_gt_notintable_1 = rx_gt_notintable[((2* 4)-1):(1* 4)]; - assign rx_gt_data_1 = rx_gt_data[((2*32)-1):(1*32)]; - assign rx_gt_charisk_2 = rx_gt_charisk[((3* 4)-1):(2* 4)]; - assign rx_gt_disperr_2 = rx_gt_disperr[((3* 4)-1):(2* 4)]; - assign rx_gt_notintable_2 = rx_gt_notintable[((3* 4)-1):(2* 4)]; - assign rx_gt_data_2 = rx_gt_data[((3*32)-1):(2*32)]; - assign rx_gt_charisk_3 = rx_gt_charisk[((4* 4)-1):(3* 4)]; - assign rx_gt_disperr_3 = rx_gt_disperr[((4* 4)-1):(3* 4)]; - assign rx_gt_notintable_3 = rx_gt_notintable[((4* 4)-1):(3* 4)]; - assign rx_gt_data_3 = rx_gt_data[((4*32)-1):(3*32)]; - assign rx_gt_charisk_4 = rx_gt_charisk[((5* 4)-1):(4* 4)]; - assign rx_gt_disperr_4 = rx_gt_disperr[((5* 4)-1):(4* 4)]; - assign rx_gt_notintable_4 = rx_gt_notintable[((5* 4)-1):(4* 4)]; - assign rx_gt_data_4 = rx_gt_data[((5*32)-1):(4*32)]; - assign rx_gt_charisk_5 = rx_gt_charisk[((6* 4)-1):(5* 4)]; - assign rx_gt_disperr_5 = rx_gt_disperr[((6* 4)-1):(5* 4)]; - assign rx_gt_notintable_5 = rx_gt_notintable[((6* 4)-1):(5* 4)]; - assign rx_gt_data_5 = rx_gt_data[((6*32)-1):(5*32)]; - assign rx_gt_charisk_6 = rx_gt_charisk[((7* 4)-1):(6* 4)]; - assign rx_gt_disperr_6 = rx_gt_disperr[((7* 4)-1):(6* 4)]; - assign rx_gt_notintable_6 = rx_gt_notintable[((7* 4)-1):(6* 4)]; - assign rx_gt_data_6 = rx_gt_data[((7*32)-1):(6*32)]; - assign rx_gt_charisk_7 = rx_gt_charisk[((8* 4)-1):(7* 4)]; - assign rx_gt_disperr_7 = rx_gt_disperr[((8* 4)-1):(7* 4)]; - assign rx_gt_notintable_7 = rx_gt_notintable[((8* 4)-1):(7* 4)]; - assign rx_gt_data_7 = rx_gt_data[((8*32)-1):(7*32)]; - - assign rx_gt_ilas_f_0 = rx_gt_ilas_f[((1* 4)-1):(0* 4)]; - assign rx_gt_ilas_q_0 = rx_gt_ilas_q[((1* 4)-1):(0* 4)]; - assign rx_gt_ilas_a_0 = rx_gt_ilas_a[((1* 4)-1):(0* 4)]; - assign rx_gt_ilas_r_0 = rx_gt_ilas_r[((1* 4)-1):(0* 4)]; - assign rx_gt_cgs_k_0 = rx_gt_cgs_k[((1* 4)-1):(0* 4)]; - assign rx_gt_ilas_f_1 = rx_gt_ilas_f[((2* 4)-1):(1* 4)]; - assign rx_gt_ilas_q_1 = rx_gt_ilas_q[((2* 4)-1):(1* 4)]; - assign rx_gt_ilas_a_1 = rx_gt_ilas_a[((2* 4)-1):(1* 4)]; - assign rx_gt_ilas_r_1 = rx_gt_ilas_r[((2* 4)-1):(1* 4)]; - assign rx_gt_cgs_k_1 = rx_gt_cgs_k[((2* 4)-1):(1* 4)]; - assign rx_gt_ilas_f_2 = rx_gt_ilas_f[((3* 4)-1):(2* 4)]; - assign rx_gt_ilas_q_2 = rx_gt_ilas_q[((3* 4)-1):(2* 4)]; - assign rx_gt_ilas_a_2 = rx_gt_ilas_a[((3* 4)-1):(2* 4)]; - assign rx_gt_ilas_r_2 = rx_gt_ilas_r[((3* 4)-1):(2* 4)]; - assign rx_gt_cgs_k_2 = rx_gt_cgs_k[((3* 4)-1):(2* 4)]; - assign rx_gt_ilas_f_3 = rx_gt_ilas_f[((4* 4)-1):(3* 4)]; - assign rx_gt_ilas_q_3 = rx_gt_ilas_q[((4* 4)-1):(3* 4)]; - assign rx_gt_ilas_a_3 = rx_gt_ilas_a[((4* 4)-1):(3* 4)]; - assign rx_gt_ilas_r_3 = rx_gt_ilas_r[((4* 4)-1):(3* 4)]; - assign rx_gt_cgs_k_3 = rx_gt_cgs_k[((4* 4)-1):(3* 4)]; - assign rx_gt_ilas_f_4 = rx_gt_ilas_f[((5* 4)-1):(4* 4)]; - assign rx_gt_ilas_q_4 = rx_gt_ilas_q[((5* 4)-1):(4* 4)]; - assign rx_gt_ilas_a_4 = rx_gt_ilas_a[((5* 4)-1):(4* 4)]; - assign rx_gt_ilas_r_4 = rx_gt_ilas_r[((5* 4)-1):(4* 4)]; - assign rx_gt_cgs_k_4 = rx_gt_cgs_k[((5* 4)-1):(4* 4)]; - assign rx_gt_ilas_f_5 = rx_gt_ilas_f[((6* 4)-1):(5* 4)]; - assign rx_gt_ilas_q_5 = rx_gt_ilas_q[((6* 4)-1):(5* 4)]; - assign rx_gt_ilas_a_5 = rx_gt_ilas_a[((6* 4)-1):(5* 4)]; - assign rx_gt_ilas_r_5 = rx_gt_ilas_r[((6* 4)-1):(5* 4)]; - assign rx_gt_cgs_k_5 = rx_gt_cgs_k[((6* 4)-1):(5* 4)]; - assign rx_gt_ilas_f_6 = rx_gt_ilas_f[((7* 4)-1):(6* 4)]; - assign rx_gt_ilas_q_6 = rx_gt_ilas_q[((7* 4)-1):(6* 4)]; - assign rx_gt_ilas_a_6 = rx_gt_ilas_a[((7* 4)-1):(6* 4)]; - assign rx_gt_ilas_r_6 = rx_gt_ilas_r[((7* 4)-1):(6* 4)]; - assign rx_gt_cgs_k_6 = rx_gt_cgs_k[((7* 4)-1):(6* 4)]; - assign rx_gt_ilas_f_7 = rx_gt_ilas_f[((8* 4)-1):(7* 4)]; - assign rx_gt_ilas_q_7 = rx_gt_ilas_q[((8* 4)-1):(7* 4)]; - assign rx_gt_ilas_a_7 = rx_gt_ilas_a[((8* 4)-1):(7* 4)]; - assign rx_gt_ilas_r_7 = rx_gt_ilas_r[((8* 4)-1):(7* 4)]; - assign rx_gt_cgs_k_7 = rx_gt_cgs_k[((8* 4)-1):(7* 4)]; - - assign tx_gt_charisk[((1* 4)-1):(0* 4)] = tx_gt_charisk_0; - assign tx_gt_data[((1*32)-1):(0*32)] = tx_gt_data_0; - assign tx_gt_charisk[((2* 4)-1):(1* 4)] = tx_gt_charisk_1; - assign tx_gt_data[((2*32)-1):(1*32)] = tx_gt_data_1; - assign tx_gt_charisk[((3* 4)-1):(2* 4)] = tx_gt_charisk_2; - assign tx_gt_data[((3*32)-1):(2*32)] = tx_gt_data_2; - assign tx_gt_charisk[((4* 4)-1):(3* 4)] = tx_gt_charisk_3; - assign tx_gt_data[((4*32)-1):(3*32)] = tx_gt_data_3; - assign tx_gt_charisk[((5* 4)-1):(4* 4)] = tx_gt_charisk_4; - assign tx_gt_data[((5*32)-1):(4*32)] = tx_gt_data_4; - assign tx_gt_charisk[((6* 4)-1):(5* 4)] = tx_gt_charisk_5; - assign tx_gt_data[((6*32)-1):(5*32)] = tx_gt_data_5; - assign tx_gt_charisk[((7* 4)-1):(6* 4)] = tx_gt_charisk_6; - assign tx_gt_data[((7*32)-1):(6*32)] = tx_gt_data_6; - assign tx_gt_charisk[((8* 4)-1):(7* 4)] = tx_gt_charisk_7; - assign tx_gt_data[((8*32)-1):(7*32)] = tx_gt_data_7; + wire qpll0_rst; + wire qpll1_rst; + wire [(( 1*8)-1):0] qpll_clk; + wire [(( 1*8)-1):0] qpll_ref_clk; + wire [(( 1*8)-1):0] qpll_locked; + wire [(( 1*8)-1):0] pll_rst; + wire [(( 1*8)-1):0] pll_rst_m; + wire [(( 1*8)-1):0] rx_out_clk; + wire [(( 1*8)-1):0] rx_clk; + wire [(( 1*8)-1):0] rx_rst; + wire [(( 1*8)-1):0] rx_sof; + wire [((32*8)-1):0] rx_data; + wire [(( 1*8)-1):0] rx_sysref; + wire [(( 1*8)-1):0] rx_sync; + wire [(( 4*8)-1):0] rx_gt_charisk; + wire [(( 4*8)-1):0] rx_gt_disperr; + wire [(( 4*8)-1):0] rx_gt_notintable; + wire [((32*8)-1):0] rx_gt_data; + wire [(( 1*8)-1):0] rx_gt_comma_align_enb; + wire [(( 4*8)-1):0] rx_gt_ilas_f; + wire [(( 4*8)-1):0] rx_gt_ilas_q; + wire [(( 4*8)-1):0] rx_gt_ilas_a; + wire [(( 4*8)-1):0] rx_gt_ilas_r; + wire [(( 4*8)-1):0] rx_gt_cgs_k; + wire [(( 1*8)-1):0] rx_ip_rst; + wire [(( 4*8)-1):0] rx_ip_sof; + wire [((32*8)-1):0] rx_ip_data; + wire [(( 1*8)-1):0] rx_ip_sysref; + wire [(( 1*8)-1):0] rx_ip_sync; + wire [(( 1*8)-1):0] rx_ip_rst_done; + wire [(( 1*8)-1):0] rx_rst_m; + wire [(( 1*8)-1):0] rx_gt_rst; + wire [(( 1*8)-1):0] rx_gt_rst_m; + wire [(( 1*8)-1):0] rx_user_ready; + wire [(( 1*8)-1):0] rx_rst_done_m; + wire [(( 1*8)-1):0] rx_pll_locked_m; + wire [(( 1*8)-1):0] rx_user_ready_m; + wire [(( 1*8)-1):0] rx_rst_done_shift; + wire [(( 1*8)-1):0] rx_rst_done; + wire [(( 1*8)-1):0] rx_pll_locked_shift; + wire [(( 1*8)-1):0] rx_pll_locked; + wire [(( 1*8)-1):0] tx_out_clk; + wire [(( 1*8)-1):0] tx_clk; + wire [(( 1*8)-1):0] tx_rst; + wire [((32*8)-1):0] tx_data; + wire [(( 1*8)-1):0] tx_sysref; + wire [(( 1*8)-1):0] tx_sync; + wire [(( 4*8)-1):0] tx_gt_charisk; + wire [((32*8)-1):0] tx_gt_data; + wire [(( 1*8)-1):0] tx_ip_rst; + wire [((32*8)-1):0] tx_ip_data; + wire [(( 1*8)-1):0] tx_ip_sysref; + wire [(( 1*8)-1):0] tx_ip_sync; + wire [(( 1*8)-1):0] tx_ip_rst_done; + wire [(( 1*8)-1):0] tx_rst_m; + wire [(( 1*8)-1):0] tx_gt_rst; + wire [(( 1*8)-1):0] tx_gt_rst_m; + wire [(( 1*8)-1):0] tx_user_ready; + wire [(( 1*8)-1):0] tx_rst_done_m; + wire [(( 1*8)-1):0] tx_pll_locked_m; + wire [(( 1*8)-1):0] tx_user_ready_m; + wire [(( 1*8)-1):0] tx_rst_done_shift; + wire [(( 1*8)-1):0] tx_rst_done; + wire [(( 1*8)-1):0] tx_pll_locked_shift; + wire [(( 1*8)-1):0] tx_pll_locked; + wire up_rstn; + wire up_clk; + wire up_wreq; + wire [((14*1)-1):0] up_waddr; + wire [((32*1)-1):0] up_wdata; + wire [(( 1*9)-1):0] up_wack; + wire up_rreq; + wire [((14*1)-1):0] up_raddr; + wire [((32*9)-1):0] up_rdata; + wire [(( 1*9)-1):0] up_rack; + wire [(( 1*8)-1):0] up_es_dma_req; + wire [((32*8)-1):0] up_es_dma_addr; + wire [((32*8)-1):0] up_es_dma_data; + wire [(( 1*8)-1):0] up_es_dma_ack; + wire [(( 1*8)-1):0] up_es_dma_err; // signal name changes assign up_rstn = axi_aresetn; assign up_clk = axi_aclk; - // drp range-extended + // split-up interfaces - assign up_status_extn_s = 9'hff; - assign rx_rst_done_extn_s = {up_status_extn_s[8:PCORE_NUM_OF_LANES], rx_rst_done_s}; - assign rx_pll_locked_extn_s = {up_status_extn_s[8:PCORE_NUM_OF_LANES], rx_pll_locked_s}; - assign tx_rst_done_extn_s = {up_status_extn_s[8:PCORE_NUM_OF_LANES], tx_rst_done_s}; - assign tx_pll_locked_extn_s = {up_status_extn_s[8:PCORE_NUM_OF_LANES], tx_pll_locked_s}; + assign rx_out_clk_0 = rx_out_clk[0]; + assign rx_rst_0 = rx_rst[0]; + assign rx_sof_0 = rx_sof[0]; + assign rx_data_0 = rx_data[((32*0)+31):(32*0)]; + assign rx_sync_0 = rx_sync[0]; + assign rx_gt_charisk_0 = rx_gt_charisk[((4*0)+3):(4*0)]; + assign rx_gt_disperr_0 = rx_gt_disperr[((4*0)+3):(4*0)]; + assign rx_gt_notintable_0 = rx_gt_notintable[((4*0)+3):(4*0)]; + assign rx_gt_data_0 = rx_gt_data[((32*0)+31):(32*0)]; + assign rx_gt_ilas_f_0 = rx_gt_ilas_f[((4*0)+3):(4*0)]; + assign rx_gt_ilas_q_0 = rx_gt_ilas_q[((4*0)+3):(4*0)]; + assign rx_gt_ilas_a_0 = rx_gt_ilas_a[((4*0)+3):(4*0)]; + assign rx_gt_ilas_r_0 = rx_gt_ilas_r[((4*0)+3):(4*0)]; + assign rx_gt_cgs_k_0 = rx_gt_cgs_k[((4*0)+3):(4*0)]; + assign rx_ip_rst_0 = rx_ip_rst[0]; + assign rx_ip_sysref_0 = rx_ip_sysref[0]; + assign rx_ip_rst_done_0 = rx_ip_rst_done[0]; - assign up_drp_rdata_s = up_drp_rdata_gt_s[15] | up_drp_rdata_gt_s[14] | - up_drp_rdata_gt_s[13] | up_drp_rdata_gt_s[12] | - up_drp_rdata_gt_s[11] | up_drp_rdata_gt_s[10] | - up_drp_rdata_gt_s[ 9] | up_drp_rdata_gt_s[ 8] | - up_drp_rdata_gt_s[ 7] | up_drp_rdata_gt_s[ 6] | - up_drp_rdata_gt_s[ 5] | up_drp_rdata_gt_s[ 4] | - up_drp_rdata_gt_s[ 3] | up_drp_rdata_gt_s[ 2] | - up_drp_rdata_gt_s[ 1] | up_drp_rdata_gt_s[ 0]; + assign rx_clk[0] = rx_clk_0; + assign rx_sysref[0] = rx_sysref_0; + assign rx_gt_comma_align_enb[0] = rx_gt_comma_align_enb_0; + assign rx_ip_sof[((4*0)+3):(4*0)] = rx_ip_sof_0; + assign rx_ip_data[((32*0)+31):(32*0)] = rx_ip_data_0; + assign rx_ip_sync[0] = rx_ip_sync_0; - assign up_drp_ready_s = up_drp_ready_gt_s[15] | up_drp_ready_gt_s[14] | - up_drp_ready_gt_s[13] | up_drp_ready_gt_s[12] | - up_drp_ready_gt_s[11] | up_drp_ready_gt_s[10] | - up_drp_ready_gt_s[ 9] | up_drp_ready_gt_s[ 8] | - up_drp_ready_gt_s[ 7] | up_drp_ready_gt_s[ 6] | - up_drp_ready_gt_s[ 5] | up_drp_ready_gt_s[ 4] | - up_drp_ready_gt_s[ 3] | up_drp_ready_gt_s[ 2] | - up_drp_ready_gt_s[ 1] | up_drp_ready_gt_s[ 0]; + assign rx_out_clk_1 = rx_out_clk[1]; + assign rx_rst_1 = rx_rst[1]; + assign rx_sof_1 = rx_sof[1]; + assign rx_data_1 = rx_data[((32*1)+31):(32*1)]; + assign rx_sync_1 = rx_sync[1]; + assign rx_gt_charisk_1 = rx_gt_charisk[((4*1)+3):(4*1)]; + assign rx_gt_disperr_1 = rx_gt_disperr[((4*1)+3):(4*1)]; + assign rx_gt_notintable_1 = rx_gt_notintable[((4*1)+3):(4*1)]; + assign rx_gt_data_1 = rx_gt_data[((32*1)+31):(32*1)]; + assign rx_gt_ilas_f_1 = rx_gt_ilas_f[((4*1)+3):(4*1)]; + assign rx_gt_ilas_q_1 = rx_gt_ilas_q[((4*1)+3):(4*1)]; + assign rx_gt_ilas_a_1 = rx_gt_ilas_a[((4*1)+3):(4*1)]; + assign rx_gt_ilas_r_1 = rx_gt_ilas_r[((4*1)+3):(4*1)]; + assign rx_gt_cgs_k_1 = rx_gt_cgs_k[((4*1)+3):(4*1)]; + assign rx_ip_rst_1 = rx_ip_rst[1]; + assign rx_ip_sysref_1 = rx_ip_sysref[1]; + assign rx_ip_rst_done_1 = rx_ip_rst_done[1]; - assign up_drp_rxrate_s = up_drp_rxrate_gt_s[15] | up_drp_rxrate_gt_s[14] | - up_drp_rxrate_gt_s[13] | up_drp_rxrate_gt_s[12] | - up_drp_rxrate_gt_s[11] | up_drp_rxrate_gt_s[10] | - up_drp_rxrate_gt_s[ 9] | up_drp_rxrate_gt_s[ 8] | - up_drp_rxrate_gt_s[ 7] | up_drp_rxrate_gt_s[ 6] | - up_drp_rxrate_gt_s[ 5] | up_drp_rxrate_gt_s[ 4] | - up_drp_rxrate_gt_s[ 3] | up_drp_rxrate_gt_s[ 2] | - up_drp_rxrate_gt_s[ 1] | up_drp_rxrate_gt_s[ 0]; + assign rx_clk[1] = rx_clk_1; + assign rx_sysref[1] = rx_sysref_1; + assign rx_gt_comma_align_enb[1] = rx_gt_comma_align_enb_1; + assign rx_ip_sof[((4*1)+3):(4*1)] = rx_ip_sof_1; + assign rx_ip_data[((32*1)+31):(32*1)] = rx_ip_data_1; + assign rx_ip_sync[1] = rx_ip_sync_1; - // asymmetric widths -- receive + assign rx_out_clk_2 = rx_out_clk[2]; + assign rx_rst_2 = rx_rst[2]; + assign rx_sof_2 = rx_sof[2]; + assign rx_data_2 = rx_data[((32*2)+31):(32*2)]; + assign rx_sync_2 = rx_sync[2]; + assign rx_gt_charisk_2 = rx_gt_charisk[((4*2)+3):(4*2)]; + assign rx_gt_disperr_2 = rx_gt_disperr[((4*2)+3):(4*2)]; + assign rx_gt_notintable_2 = rx_gt_notintable[((4*2)+3):(4*2)]; + assign rx_gt_data_2 = rx_gt_data[((32*2)+31):(32*2)]; + assign rx_gt_ilas_f_2 = rx_gt_ilas_f[((4*2)+3):(4*2)]; + assign rx_gt_ilas_q_2 = rx_gt_ilas_q[((4*2)+3):(4*2)]; + assign rx_gt_ilas_a_2 = rx_gt_ilas_a[((4*2)+3):(4*2)]; + assign rx_gt_ilas_r_2 = rx_gt_ilas_r[((4*2)+3):(4*2)]; + assign rx_gt_cgs_k_2 = rx_gt_cgs_k[((4*2)+3):(4*2)]; + assign rx_ip_rst_2 = rx_ip_rst[2]; + assign rx_ip_sysref_2 = rx_ip_sysref[2]; + assign rx_ip_rst_done_2 = rx_ip_rst_done[2]; - assign rx_data = rx_data_s[((PCORE_NUM_OF_RX_LANES*32)-1):0]; - assign rx_sof = rx_sof_s[((PCORE_NUM_OF_RX_LANES* 1)-1):0]; + assign rx_clk[2] = rx_clk_2; + assign rx_sysref[2] = rx_sysref_2; + assign rx_gt_comma_align_enb[2] = rx_gt_comma_align_enb_2; + assign rx_ip_sof[((4*2)+3):(4*2)] = rx_ip_sof_2; + assign rx_ip_data[((32*2)+31):(32*2)] = rx_ip_data_2; + assign rx_ip_sync[2] = rx_ip_sync_2; - generate - if (PCORE_NUM_OF_LANES < 8) begin - assign rx_gt_charisk[((8*4)-1):(PCORE_NUM_OF_LANES*4)] = 'd0; - assign rx_gt_disperr[((8*4)-1):(PCORE_NUM_OF_LANES*4)] = 'd0; - assign rx_gt_notintable[((8*4)-1):(PCORE_NUM_OF_LANES*4)] = 'd0; - assign rx_gt_data[((8*32)-1):(PCORE_NUM_OF_LANES*32)] = 'd0; - assign rx_gt_charisk[((PCORE_NUM_OF_LANES*4)-1):0] = rx_gt_charisk_s; - assign rx_gt_disperr[((PCORE_NUM_OF_LANES*4)-1):0] = rx_gt_disperr_s; - assign rx_gt_notintable[((PCORE_NUM_OF_LANES*4)-1):0] = rx_gt_notintable_s; - assign rx_gt_data[((PCORE_NUM_OF_LANES*32)-1):0] = rx_gt_data_s; - end else begin - assign rx_gt_charisk = rx_gt_charisk_s[((8*4)-1):0]; - assign rx_gt_disperr = rx_gt_disperr_s[((8*4)-1):0]; - assign rx_gt_notintable = rx_gt_notintable_s[((8*4)-1):0]; - assign rx_gt_data = rx_gt_data_s[((8*32)-1):0]; - end - endgenerate + assign rx_out_clk_3 = rx_out_clk[3]; + assign rx_rst_3 = rx_rst[3]; + assign rx_sof_3 = rx_sof[3]; + assign rx_data_3 = rx_data[((32*3)+31):(32*3)]; + assign rx_sync_3 = rx_sync[3]; + assign rx_gt_charisk_3 = rx_gt_charisk[((4*3)+3):(4*3)]; + assign rx_gt_disperr_3 = rx_gt_disperr[((4*3)+3):(4*3)]; + assign rx_gt_notintable_3 = rx_gt_notintable[((4*3)+3):(4*3)]; + assign rx_gt_data_3 = rx_gt_data[((32*3)+31):(32*3)]; + assign rx_gt_ilas_f_3 = rx_gt_ilas_f[((4*3)+3):(4*3)]; + assign rx_gt_ilas_q_3 = rx_gt_ilas_q[((4*3)+3):(4*3)]; + assign rx_gt_ilas_a_3 = rx_gt_ilas_a[((4*3)+3):(4*3)]; + assign rx_gt_ilas_r_3 = rx_gt_ilas_r[((4*3)+3):(4*3)]; + assign rx_gt_cgs_k_3 = rx_gt_cgs_k[((4*3)+3):(4*3)]; + assign rx_ip_rst_3 = rx_ip_rst[3]; + assign rx_ip_sysref_3 = rx_ip_sysref[3]; + assign rx_ip_rst_done_3 = rx_ip_rst_done[3]; - generate - if (PCORE_NUM_OF_LANES < 8) begin - assign rx_gt_ilas_f[((8*4)-1):(PCORE_NUM_OF_LANES*4)] = 'd0; - assign rx_gt_ilas_q[((8*4)-1):(PCORE_NUM_OF_LANES*4)] = 'd0; - assign rx_gt_ilas_a[((8*4)-1):(PCORE_NUM_OF_LANES*4)] = 'd0; - assign rx_gt_ilas_r[((8*4)-1):(PCORE_NUM_OF_LANES*4)] = 'd0; - assign rx_gt_cgs_k[((8*4)-1):(PCORE_NUM_OF_LANES*4)] = 'd0; - assign rx_gt_ilas_f[((PCORE_NUM_OF_LANES*4)-1):0] = rx_gt_ilas_f_s; - assign rx_gt_ilas_q[((PCORE_NUM_OF_LANES*4)-1):0] = rx_gt_ilas_q_s; - assign rx_gt_ilas_a[((PCORE_NUM_OF_LANES*4)-1):0] = rx_gt_ilas_a_s; - assign rx_gt_ilas_r[((PCORE_NUM_OF_LANES*4)-1):0] = rx_gt_ilas_r_s; - assign rx_gt_cgs_k[((PCORE_NUM_OF_LANES*4)-1):0] = rx_gt_cgs_k_s; - end else begin - assign rx_gt_ilas_f = rx_gt_ilas_f_s[((8*4)-1):0]; - assign rx_gt_ilas_q = rx_gt_ilas_q_s[((8*4)-1):0]; - assign rx_gt_ilas_a = rx_gt_ilas_a_s[((8*4)-1):0]; - assign rx_gt_ilas_r = rx_gt_ilas_r_s[((8*4)-1):0]; - assign rx_gt_cgs_k = rx_gt_cgs_k_s[((8*4)-1):0]; - end - endgenerate + assign rx_clk[3] = rx_clk_3; + assign rx_sysref[3] = rx_sysref_3; + assign rx_gt_comma_align_enb[3] = rx_gt_comma_align_enb_3; + assign rx_ip_sof[((4*3)+3):(4*3)] = rx_ip_sof_3; + assign rx_ip_data[((32*3)+31):(32*3)] = rx_ip_data_3; + assign rx_ip_sync[3] = rx_ip_sync_3; - generate - if (PCORE_NUM_OF_LANES == PCORE_NUM_OF_RX_LANES) begin - assign rx_data_p_s = rx_data_p; - assign rx_data_n_s = rx_data_n; - assign rx_ip_data_s = rx_ip_data; - end else begin - assign rx_data_p_s[((PCORE_NUM_OF_LANES* 1)-1):(PCORE_NUM_OF_RX_LANES* 1)] = 'd0; - assign rx_data_n_s[((PCORE_NUM_OF_LANES* 1)-1):(PCORE_NUM_OF_RX_LANES* 1)] = 'd0; - assign rx_ip_data_s[((PCORE_NUM_OF_LANES*32)-1):(PCORE_NUM_OF_RX_LANES*32)] = 'd0; - assign rx_data_p_s[((PCORE_NUM_OF_RX_LANES* 1)-1):0] = rx_data_p; - assign rx_data_n_s[((PCORE_NUM_OF_RX_LANES* 1)-1):0] = rx_data_n; - assign rx_ip_data_s[((PCORE_NUM_OF_RX_LANES*32)-1):0] = rx_ip_data; - end - endgenerate + assign rx_out_clk_4 = rx_out_clk[4]; + assign rx_rst_4 = rx_rst[4]; + assign rx_sof_4 = rx_sof[4]; + assign rx_data_4 = rx_data[((32*4)+31):(32*4)]; + assign rx_sync_4 = rx_sync[4]; + assign rx_gt_charisk_4 = rx_gt_charisk[((4*4)+3):(4*4)]; + assign rx_gt_disperr_4 = rx_gt_disperr[((4*4)+3):(4*4)]; + assign rx_gt_notintable_4 = rx_gt_notintable[((4*4)+3):(4*4)]; + assign rx_gt_data_4 = rx_gt_data[((32*4)+31):(32*4)]; + assign rx_gt_ilas_f_4 = rx_gt_ilas_f[((4*4)+3):(4*4)]; + assign rx_gt_ilas_q_4 = rx_gt_ilas_q[((4*4)+3):(4*4)]; + assign rx_gt_ilas_a_4 = rx_gt_ilas_a[((4*4)+3):(4*4)]; + assign rx_gt_ilas_r_4 = rx_gt_ilas_r[((4*4)+3):(4*4)]; + assign rx_gt_cgs_k_4 = rx_gt_cgs_k[((4*4)+3):(4*4)]; + assign rx_ip_rst_4 = rx_ip_rst[4]; + assign rx_ip_sysref_4 = rx_ip_sysref[4]; + assign rx_ip_rst_done_4 = rx_ip_rst_done[4]; - // asymmetric widths -- transmit + assign rx_clk[4] = rx_clk_4; + assign rx_sysref[4] = rx_sysref_4; + assign rx_gt_comma_align_enb[4] = rx_gt_comma_align_enb_4; + assign rx_ip_sof[((4*4)+3):(4*4)] = rx_ip_sof_4; + assign rx_ip_data[((32*4)+31):(32*4)] = rx_ip_data_4; + assign rx_ip_sync[4] = rx_ip_sync_4; - assign tx_data_p = tx_data_p_s[((PCORE_NUM_OF_TX_LANES* 1)-1):0]; - assign tx_data_n = tx_data_n_s[((PCORE_NUM_OF_TX_LANES* 1)-1):0]; + assign rx_out_clk_5 = rx_out_clk[5]; + assign rx_rst_5 = rx_rst[5]; + assign rx_sof_5 = rx_sof[5]; + assign rx_data_5 = rx_data[((32*5)+31):(32*5)]; + assign rx_sync_5 = rx_sync[5]; + assign rx_gt_charisk_5 = rx_gt_charisk[((4*5)+3):(4*5)]; + assign rx_gt_disperr_5 = rx_gt_disperr[((4*5)+3):(4*5)]; + assign rx_gt_notintable_5 = rx_gt_notintable[((4*5)+3):(4*5)]; + assign rx_gt_data_5 = rx_gt_data[((32*5)+31):(32*5)]; + assign rx_gt_ilas_f_5 = rx_gt_ilas_f[((4*5)+3):(4*5)]; + assign rx_gt_ilas_q_5 = rx_gt_ilas_q[((4*5)+3):(4*5)]; + assign rx_gt_ilas_a_5 = rx_gt_ilas_a[((4*5)+3):(4*5)]; + assign rx_gt_ilas_r_5 = rx_gt_ilas_r[((4*5)+3):(4*5)]; + assign rx_gt_cgs_k_5 = rx_gt_cgs_k[((4*5)+3):(4*5)]; + assign rx_ip_rst_5 = rx_ip_rst[5]; + assign rx_ip_sysref_5 = rx_ip_sysref[5]; + assign rx_ip_rst_done_5 = rx_ip_rst_done[5]; - generate - if (PCORE_NUM_OF_LANES > 8) begin - end else begin - end - endgenerate + assign rx_clk[5] = rx_clk_5; + assign rx_sysref[5] = rx_sysref_5; + assign rx_gt_comma_align_enb[5] = rx_gt_comma_align_enb_5; + assign rx_ip_sof[((4*5)+3):(4*5)] = rx_ip_sof_5; + assign rx_ip_data[((32*5)+31):(32*5)] = rx_ip_data_5; + assign rx_ip_sync[5] = rx_ip_sync_5; - generate - if (PCORE_NUM_OF_LANES > 8) begin - assign tx_gt_charisk_s[((PCORE_NUM_OF_LANES* 4)-1):(8* 4)] = 'd0; - assign tx_gt_data_s[((PCORE_NUM_OF_LANES*32)-1):(8*32)] = 'd0; - assign tx_gt_charisk_s[((8* 4)-1):0] = tx_gt_charisk; - assign tx_gt_data_s[((8*32)-1):0] = tx_gt_data; - end else begin - assign tx_gt_charisk_s = tx_gt_charisk[((PCORE_NUM_OF_LANES* 4)-1):0]; - assign tx_gt_data_s = tx_gt_data[((PCORE_NUM_OF_LANES*32)-1):0]; - end - endgenerate + assign rx_out_clk_6 = rx_out_clk[6]; + assign rx_rst_6 = rx_rst[6]; + assign rx_sof_6 = rx_sof[6]; + assign rx_data_6 = rx_data[((32*6)+31):(32*6)]; + assign rx_sync_6 = rx_sync[6]; + assign rx_gt_charisk_6 = rx_gt_charisk[((4*6)+3):(4*6)]; + assign rx_gt_disperr_6 = rx_gt_disperr[((4*6)+3):(4*6)]; + assign rx_gt_notintable_6 = rx_gt_notintable[((4*6)+3):(4*6)]; + assign rx_gt_data_6 = rx_gt_data[((32*6)+31):(32*6)]; + assign rx_gt_ilas_f_6 = rx_gt_ilas_f[((4*6)+3):(4*6)]; + assign rx_gt_ilas_q_6 = rx_gt_ilas_q[((4*6)+3):(4*6)]; + assign rx_gt_ilas_a_6 = rx_gt_ilas_a[((4*6)+3):(4*6)]; + assign rx_gt_ilas_r_6 = rx_gt_ilas_r[((4*6)+3):(4*6)]; + assign rx_gt_cgs_k_6 = rx_gt_cgs_k[((4*6)+3):(4*6)]; + assign rx_ip_rst_6 = rx_ip_rst[6]; + assign rx_ip_sysref_6 = rx_ip_sysref[6]; + assign rx_ip_rst_done_6 = rx_ip_rst_done[6]; - // transmit data interleave -- since transceivers are shared, lane assignments may not match pin assignments + assign rx_clk[6] = rx_clk_6; + assign rx_sysref[6] = rx_sysref_6; + assign rx_gt_comma_align_enb[6] = rx_gt_comma_align_enb_6; + assign rx_ip_sof[((4*6)+3):(4*6)] = rx_ip_sof_6; + assign rx_ip_data[((32*6)+31):(32*6)] = rx_ip_data_6; + assign rx_ip_sync[6] = rx_ip_sync_6; - assign tx_ip_data = tx_data; + assign rx_out_clk_7 = rx_out_clk[7]; + assign rx_rst_7 = rx_rst[7]; + assign rx_sof_7 = rx_sof[7]; + assign rx_data_7 = rx_data[((32*7)+31):(32*7)]; + assign rx_sync_7 = rx_sync[7]; + assign rx_gt_charisk_7 = rx_gt_charisk[((4*7)+3):(4*7)]; + assign rx_gt_disperr_7 = rx_gt_disperr[((4*7)+3):(4*7)]; + assign rx_gt_notintable_7 = rx_gt_notintable[((4*7)+3):(4*7)]; + assign rx_gt_data_7 = rx_gt_data[((32*7)+31):(32*7)]; + assign rx_gt_ilas_f_7 = rx_gt_ilas_f[((4*7)+3):(4*7)]; + assign rx_gt_ilas_q_7 = rx_gt_ilas_q[((4*7)+3):(4*7)]; + assign rx_gt_ilas_a_7 = rx_gt_ilas_a[((4*7)+3):(4*7)]; + assign rx_gt_ilas_r_7 = rx_gt_ilas_r[((4*7)+3):(4*7)]; + assign rx_gt_cgs_k_7 = rx_gt_cgs_k[((4*7)+3):(4*7)]; + assign rx_ip_rst_7 = rx_ip_rst[7]; + assign rx_ip_sysref_7 = rx_ip_sysref[7]; + assign rx_ip_rst_done_7 = rx_ip_rst_done[7]; - assign tx_gt_data_extn_zero_s = 288'd0; - assign tx_gt_charisk_extn_zero_s = 36'd0; - assign tx_gt_data_extn_s = {tx_gt_data_extn_zero_s[(((9-PCORE_NUM_OF_LANES)*32)-1):0], tx_gt_data_s}; - assign tx_gt_charisk_extn_s = {tx_gt_charisk_extn_zero_s[(((9-PCORE_NUM_OF_LANES)*4)-1):0], tx_gt_charisk_s}; + assign rx_clk[7] = rx_clk_7; + assign rx_sysref[7] = rx_sysref_7; + assign rx_gt_comma_align_enb[7] = rx_gt_comma_align_enb_7; + assign rx_ip_sof[((4*7)+3):(4*7)] = rx_ip_sof_7; + assign rx_ip_data[((32*7)+31):(32*7)] = rx_ip_data_7; + assign rx_ip_sync[7] = rx_ip_sync_7; - assign tx_gt_data_mux_s[((8*32)+31):(8*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_8*32)+31):(PCORE_TX_LANE_SEL_8*32)]; - assign tx_gt_data_mux_s[((7*32)+31):(7*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_7*32)+31):(PCORE_TX_LANE_SEL_7*32)]; - assign tx_gt_data_mux_s[((6*32)+31):(6*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_6*32)+31):(PCORE_TX_LANE_SEL_6*32)]; - assign tx_gt_data_mux_s[((5*32)+31):(5*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_5*32)+31):(PCORE_TX_LANE_SEL_5*32)]; - assign tx_gt_data_mux_s[((4*32)+31):(4*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_4*32)+31):(PCORE_TX_LANE_SEL_4*32)]; - assign tx_gt_data_mux_s[((3*32)+31):(3*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_3*32)+31):(PCORE_TX_LANE_SEL_3*32)]; - assign tx_gt_data_mux_s[((2*32)+31):(2*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_2*32)+31):(PCORE_TX_LANE_SEL_2*32)]; - assign tx_gt_data_mux_s[((1*32)+31):(1*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_1*32)+31):(PCORE_TX_LANE_SEL_1*32)]; - assign tx_gt_data_mux_s[((0*32)+31):(0*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_0*32)+31):(PCORE_TX_LANE_SEL_0*32)]; - assign tx_gt_charisk_mux_s[((8*4)+3):(8*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_8*4)+3):(PCORE_TX_LANE_SEL_8*4)]; - assign tx_gt_charisk_mux_s[((7*4)+3):(7*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_7*4)+3):(PCORE_TX_LANE_SEL_7*4)]; - assign tx_gt_charisk_mux_s[((6*4)+3):(6*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_6*4)+3):(PCORE_TX_LANE_SEL_6*4)]; - assign tx_gt_charisk_mux_s[((5*4)+3):(5*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_5*4)+3):(PCORE_TX_LANE_SEL_5*4)]; - assign tx_gt_charisk_mux_s[((4*4)+3):(4*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_4*4)+3):(PCORE_TX_LANE_SEL_4*4)]; - assign tx_gt_charisk_mux_s[((3*4)+3):(3*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_3*4)+3):(PCORE_TX_LANE_SEL_3*4)]; - assign tx_gt_charisk_mux_s[((2*4)+3):(2*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_2*4)+3):(PCORE_TX_LANE_SEL_2*4)]; - assign tx_gt_charisk_mux_s[((1*4)+3):(1*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_1*4)+3):(PCORE_TX_LANE_SEL_1*4)]; - assign tx_gt_charisk_mux_s[((0*4)+3):(0*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_0*4)+3):(PCORE_TX_LANE_SEL_0*4)]; + assign tx_out_clk_0 = tx_out_clk[0]; + assign tx_rst_0 = tx_rst[0]; + assign tx_ip_rst_0 = tx_ip_rst[0]; + assign tx_ip_data_0 = tx_ip_data[((32*0)+31):(32*0)]; + assign tx_ip_sysref_0 = tx_ip_sysref[0]; + assign tx_ip_sync_0 = tx_ip_sync[0]; + assign tx_ip_rst_done_0 = tx_ip_rst_done[0]; - // clock buffers + assign tx_clk[0] = tx_clk_0; + assign tx_data[((32*0)+31):(32*0)] = tx_data_0; + assign tx_sysref[0] = tx_sysref_0; + assign tx_sync[0] = tx_sync_0; + assign tx_gt_charisk[((4*0)+3):(4*0)] = tx_gt_charisk_0; + assign tx_gt_data[((32*0)+31):(32*0)] = tx_gt_data_0; - generate - if (PCORE_DEVICE_TYPE == 0) begin - BUFG i_bufg_rx_clk ( - .I (rx_out_clk[0]), - .O (rx_clk_g)); + assign tx_out_clk_1 = tx_out_clk[1]; + assign tx_rst_1 = tx_rst[1]; + assign tx_ip_rst_1 = tx_ip_rst[1]; + assign tx_ip_data_1 = tx_ip_data[((32*1)+31):(32*1)]; + assign tx_ip_sysref_1 = tx_ip_sysref[1]; + assign tx_ip_sync_1 = tx_ip_sync[1]; + assign tx_ip_rst_done_1 = tx_ip_rst_done[1]; + + assign tx_clk[1] = tx_clk_1; + assign tx_data[((32*1)+31):(32*1)] = tx_data_1; + assign tx_sysref[1] = tx_sysref_1; + assign tx_sync[1] = tx_sync_1; + assign tx_gt_charisk[((4*1)+3):(4*1)] = tx_gt_charisk_1; + assign tx_gt_data[((32*1)+31):(32*1)] = tx_gt_data_1; + + assign tx_out_clk_2 = tx_out_clk[2]; + assign tx_rst_2 = tx_rst[2]; + assign tx_ip_rst_2 = tx_ip_rst[2]; + assign tx_ip_data_2 = tx_ip_data[((32*2)+31):(32*2)]; + assign tx_ip_sysref_2 = tx_ip_sysref[2]; + assign tx_ip_sync_2 = tx_ip_sync[2]; + assign tx_ip_rst_done_2 = tx_ip_rst_done[2]; + + assign tx_clk[2] = tx_clk_2; + assign tx_data[((32*2)+31):(32*2)] = tx_data_2; + assign tx_sysref[2] = tx_sysref_2; + assign tx_sync[2] = tx_sync_2; + assign tx_gt_charisk[((4*2)+3):(4*2)] = tx_gt_charisk_2; + assign tx_gt_data[((32*2)+31):(32*2)] = tx_gt_data_2; + + assign tx_out_clk_3 = tx_out_clk[3]; + assign tx_rst_3 = tx_rst[3]; + assign tx_ip_rst_3 = tx_ip_rst[3]; + assign tx_ip_data_3 = tx_ip_data[((32*3)+31):(32*3)]; + assign tx_ip_sysref_3 = tx_ip_sysref[3]; + assign tx_ip_sync_3 = tx_ip_sync[3]; + assign tx_ip_rst_done_3 = tx_ip_rst_done[3]; + + assign tx_clk[3] = tx_clk_3; + assign tx_data[((32*3)+31):(32*3)] = tx_data_3; + assign tx_sysref[3] = tx_sysref_3; + assign tx_sync[3] = tx_sync_3; + assign tx_gt_charisk[((4*3)+3):(4*3)] = tx_gt_charisk_3; + assign tx_gt_data[((32*3)+31):(32*3)] = tx_gt_data_3; + + assign tx_out_clk_4 = tx_out_clk[4]; + assign tx_rst_4 = tx_rst[4]; + assign tx_ip_rst_4 = tx_ip_rst[4]; + assign tx_ip_data_4 = tx_ip_data[((32*4)+31):(32*4)]; + assign tx_ip_sysref_4 = tx_ip_sysref[4]; + assign tx_ip_sync_4 = tx_ip_sync[4]; + assign tx_ip_rst_done_4 = tx_ip_rst_done[4]; + + assign tx_clk[4] = tx_clk_4; + assign tx_data[((32*4)+31):(32*4)] = tx_data_4; + assign tx_sysref[4] = tx_sysref_4; + assign tx_sync[4] = tx_sync_4; + assign tx_gt_charisk[((4*4)+3):(4*4)] = tx_gt_charisk_4; + assign tx_gt_data[((32*4)+31):(32*4)] = tx_gt_data_4; + + assign tx_out_clk_5 = tx_out_clk[5]; + assign tx_rst_5 = tx_rst[5]; + assign tx_ip_rst_5 = tx_ip_rst[5]; + assign tx_ip_data_5 = tx_ip_data[((32*5)+31):(32*5)]; + assign tx_ip_sysref_5 = tx_ip_sysref[5]; + assign tx_ip_sync_5 = tx_ip_sync[5]; + assign tx_ip_rst_done_5 = tx_ip_rst_done[5]; + + assign tx_clk[5] = tx_clk_5; + assign tx_data[((32*5)+31):(32*5)] = tx_data_5; + assign tx_sysref[5] = tx_sysref_5; + assign tx_sync[5] = tx_sync_5; + assign tx_gt_charisk[((4*5)+3):(4*5)] = tx_gt_charisk_5; + assign tx_gt_data[((32*5)+31):(32*5)] = tx_gt_data_5; + + assign tx_out_clk_6 = tx_out_clk[6]; + assign tx_rst_6 = tx_rst[6]; + assign tx_ip_rst_6 = tx_ip_rst[6]; + assign tx_ip_data_6 = tx_ip_data[((32*6)+31):(32*6)]; + assign tx_ip_sysref_6 = tx_ip_sysref[6]; + assign tx_ip_sync_6 = tx_ip_sync[6]; + assign tx_ip_rst_done_6 = tx_ip_rst_done[6]; + + assign tx_clk[6] = tx_clk_6; + assign tx_data[((32*6)+31):(32*6)] = tx_data_6; + assign tx_sysref[6] = tx_sysref_6; + assign tx_sync[6] = tx_sync_6; + assign tx_gt_charisk[((4*6)+3):(4*6)] = tx_gt_charisk_6; + assign tx_gt_data[((32*6)+31):(32*6)] = tx_gt_data_6; + + assign tx_out_clk_7 = tx_out_clk[7]; + assign tx_rst_7 = tx_rst[7]; + assign tx_ip_rst_7 = tx_ip_rst[7]; + assign tx_ip_data_7 = tx_ip_data[((32*7)+31):(32*7)]; + assign tx_ip_sysref_7 = tx_ip_sysref[7]; + assign tx_ip_sync_7 = tx_ip_sync[7]; + assign tx_ip_rst_done_7 = tx_ip_rst_done[7]; + + assign tx_clk[7] = tx_clk_7; + assign tx_data[((32*7)+31):(32*7)] = tx_data_7; + assign tx_sysref[7] = tx_sysref_7; + assign tx_sync[7] = tx_sync_7; + assign tx_gt_charisk[((4*7)+3):(4*7)] = tx_gt_charisk_7; + assign tx_gt_data[((32*7)+31):(32*7)] = tx_gt_data_7; + + assign qpll0_rst = pll_rst[QPLL0_MSEL]; + assign qpll1_rst = pll_rst[QPLL1_MSEL]; + + assign rx_rst_done_shift = {rx_rst_done[0], rx_rst_done[7:1]}; + assign rx_pll_locked_shift = {rx_pll_locked[0], rx_pll_locked[7:1]}; + assign tx_rst_done_shift = {tx_rst_done[0], tx_rst_done[7:1]}; + assign tx_pll_locked_shift = {tx_pll_locked[0], tx_pll_locked[7:1]}; + + // up signals + + always @(posedge up_clk or negedge up_rstn) begin + if (up_rstn == 1'b0) begin + up_wack_d <= 1'd0; + up_rack_d <= 1'd0; + up_rdata_d <= 32'd0; + end else begin + up_wack_d <= | up_wack; + up_rack_d <= | up_rack; + up_rdata_d <= up_rdata[((32*0)+31):(32*0)] | + up_rdata[((32*1)+31):(32*1)] | + up_rdata[((32*2)+31):(32*2)] | + up_rdata[((32*3)+31):(32*3)] | + up_rdata[((32*4)+31):(32*4)] | + up_rdata[((32*5)+31):(32*5)] | + up_rdata[((32*6)+31):(32*6)] | + up_rdata[((32*7)+31):(32*7)] | + up_rdata[((32*8)+31):(32*8)]; + end end - if (PCORE_DEVICE_TYPE == 0) begin - BUFG i_bufg_tx_clk ( - .I (tx_out_clk[0]), - .O (tx_clk_g)); - end - - if (PCORE_DEVICE_TYPE == 1) begin - BUFG_GT i_bufg_rx_clk ( - .I (rx_out_clk[0]), - .O (rx_clk_g)); - end - - if (PCORE_DEVICE_TYPE == 1) begin - BUFG_GT i_bufg_tx_clk ( - .I (tx_out_clk[0]), - .O (tx_clk_g)); - end - endgenerate - - // transceivers - - assign qpll_clk = {{4{qpll_clk_1}}, {4{qpll_clk_0}}}; - assign qpll_ref_clk = {{4{qpll_ref_clk_1}}, {4{qpll_ref_clk_0}}}; - assign qpll_locked_s = {{4{qpll_locked_1_s}}, {4{qpll_locked_0_s}}}; - - ad_gt_common_1 #( - .DRP_ID (14), - .GTH_GTX_N (PCORE_DEVICE_TYPE), - .QPLL_REFCLK_DIV (PCORE_QPLL_REFCLK_DIV), - .QPLL_CFG (PCORE_QPLL_CFG), - .QPLL_FBDIV_RATIO (PCORE_QPLL_FBDIV_RATIO), - .QPLL_FBDIV (PCORE_QPLL_FBDIV)) - i_gt_common_1 ( - .rst (gt_pll_rst), - .ref_clk (ref_clk_q), - .qpll_clk (qpll_clk_0), - .qpll_ref_clk (qpll_ref_clk_0), - .qpll_locked (qpll_locked_0_s), - .up_clk (up_clk), - .up_drp_sel (up_drp_sel_s), - .up_drp_addr (up_drp_addr_s), - .up_drp_wr (up_drp_wr_s), - .up_drp_wdata (up_drp_wdata_s), - .up_drp_rdata (up_drp_rdata_gt_s[14]), - .up_drp_ready (up_drp_ready_gt_s[14]), - .up_drp_lanesel (up_drp_lanesel_s), - .up_drp_rxrate (up_drp_rxrate_gt_s[14])); - - ad_gt_common_1 #( - .DRP_ID (15), - .GTH_GTX_N (PCORE_DEVICE_TYPE), - .QPLL_REFCLK_DIV (PCORE_QPLL_REFCLK_DIV), - .QPLL_CFG (PCORE_QPLL_CFG), - .QPLL_FBDIV_RATIO (PCORE_QPLL_FBDIV_RATIO), - .QPLL_FBDIV (PCORE_QPLL_FBDIV)) - i_gt_common_2 ( - .rst (gt_pll_rst), - .ref_clk (ref_clk_q), - .qpll_clk (qpll_clk_1), - .qpll_ref_clk (qpll_ref_clk_1), - .qpll_locked (qpll_locked_1_s), - .up_clk (up_clk), - .up_drp_sel (up_drp_sel_s), - .up_drp_addr (up_drp_addr_s), - .up_drp_wr (up_drp_wr_s), - .up_drp_wdata (up_drp_wdata_s), - .up_drp_rdata (up_drp_rdata_gt_s[15]), - .up_drp_ready (up_drp_ready_gt_s[15]), - .up_drp_lanesel (up_drp_lanesel_s), - .up_drp_rxrate (up_drp_rxrate_gt_s[15])); + // instantiations genvar n; generate - for (n = PCORE_NUM_OF_LANES; n < 14; n = n + 1) begin: g_unused_1 - assign up_drp_rdata_gt_s[n] = 'd0; - assign up_drp_ready_gt_s[n] = 'd0; - assign up_drp_rxrate_gt_s[n] = 'd0; + for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_msel_1 + assign pll_rst_m[n] = pll_rst[PLL_MSEL[n]]; + assign rx_rst_m[n] = rx_rst[RX_MSEL[n]]; + assign rx_gt_rst_m[n] = rx_gt_rst[RX_MSEL[n]]; + assign rx_rst_done_m[n] = rx_rst_done[RX_MSEL[n]]; + assign rx_pll_locked_m[n] = rx_pll_locked[RX_MSEL[n]]; + assign rx_user_ready_m[n] = rx_user_ready[RX_MSEL[n]]; + assign tx_rst_m[n] = tx_rst[TX_MSEL[n]]; + assign tx_gt_rst_m[n] = tx_gt_rst[TX_MSEL[n]]; + assign tx_rst_done_m[n] = tx_rst_done[TX_MSEL[n]]; + assign tx_pll_locked_m[n] = tx_pll_locked[TX_MSEL[n]]; + assign tx_user_ready_m[n] = tx_user_ready[TX_MSEL[n]]; end - for (n = 0; n < PCORE_NUM_OF_LANES; n = n + 1) begin: g_lane_1 - - ad_jesd_align i_jesd_align ( - .rx_clk (rx_clk), - .rx_ip_sof (rx_ip_sof), - .rx_ip_data (rx_ip_data_s[n*32+31:n*32]), - .rx_sof (rx_sof_s[n]), - .rx_data (rx_data_s[n*32+31:n*32])); + if (NUM_OF_LANES < 8) begin + for (n = (NUM_OF_LANES-1); n < 8; n = n + 1) begin: g_unused_1 + end + end + for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lane_1 ad_gt_channel_1 #( - .DRP_ID (n), - .GTH_GTX_N (PCORE_DEVICE_TYPE), - .CPLL_FBDIV (PCORE_CPLL_FBDIV), - .RX_OUT_DIV (PCORE_RX_OUT_DIV), - .TX_OUT_DIV (PCORE_TX_OUT_DIV), - .RX_CLK25_DIV (PCORE_RX_CLK25_DIV), - .TX_CLK25_DIV (PCORE_TX_CLK25_DIV), - .PMA_RSV (PCORE_PMA_RSV), - .RX_CDR_CFG (PCORE_RX_CDR_CFG)) - i_gt_channel_1 ( - .ref_clk (ref_clk_c), - .lpm_dfe_n (up_lpm_dfe_n_s), - .cpll_pd (up_cpll_pd_s), - .cpll_rst (gt_pll_rst), - .qpll_clk (qpll_clk[n]), + .ID (n), + .GTH_GTX_N (GTH_GTX_N), + .PMA_RSV (PMA_RSV[n]), + .CPLL_FBDIV (CPLL_FBDIV[n]), + .RX_OUT_DIV (RX_OUT_DIV[n]), + .RX_CLK25_DIV (RX_CLK25_DIV[n]), + .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE[n]), + .RX_PRIMARY (RX_PRIMARY[n]), + .RX_CDR_CFG (RX_CDR_CFG[n]), + .TX_OUT_DIV (TX_OUT_DIV[n]), + .TX_CLK25_DIV (TX_CLK25_DIV[n]), + .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE[n]), + .TX_PRIMARY (TX_PRIMARY[n])) + i_channel ( + .cpll_ref_clk_in (cpll_ref_clk_in), .qpll_ref_clk (qpll_ref_clk[n]), - .qpll_locked (qpll_locked_s[n]), - .rx_rst (gt_rx_rst), - .rx_p (rx_data_p_s[n]), - .rx_n (rx_data_n_s[n]), - .rx_sys_clk_sel (up_rx_sys_clk_sel_s), - .rx_out_clk_sel (up_rx_out_clk_sel_s), + .qpll_locked (qpll_locked[n]), + .qpll_clk (qpll_clk[n]), + .pll_rst (pll_rst[n]), + .pll_rst_m (pll_rst_m[n]), + .rx_p (rx_p[n]), + .rx_n (rx_n[n]), .rx_out_clk (rx_out_clk[n]), - .rx_rst_done (rx_rst_done_s[n]), - .rx_pll_locked (rx_pll_locked_s[n]), - .rx_clk (rx_clk), - .rx_charisk (rx_gt_charisk_s[n*4+3:n*4]), - .rx_disperr (rx_gt_disperr_s[n*4+3:n*4]), - .rx_notintable (rx_gt_notintable_s[n*4+3:n*4]), - .rx_data (rx_gt_data_s[n*32+31:n*32]), - .rx_comma_align_enb (rx_ip_comma_align), - .rx_ilas_f (rx_gt_ilas_f_s[n*4+3:n*4]), - .rx_ilas_q (rx_gt_ilas_q_s[n*4+3:n*4]), - .rx_ilas_a (rx_gt_ilas_a_s[n*4+3:n*4]), - .rx_ilas_r (rx_gt_ilas_r_s[n*4+3:n*4]), - .rx_cgs_k (rx_gt_cgs_k_s[n*4+3:n*4]), - .tx_rst (gt_tx_rst), - .tx_p (tx_data_p_s[n]), - .tx_n (tx_data_n_s[n]), - .tx_sys_clk_sel (up_tx_sys_clk_sel_s), - .tx_out_clk_sel (up_tx_out_clk_sel_s), + .rx_clk (rx_clk[n]), + .rx_rst (rx_rst[n]), + .rx_rst_m (rx_rst_m[n]), + .rx_sof (rx_sof[n]), + .rx_data (rx_data[((32*n)+31):(32*n)]), + .rx_sysref (rx_sysref[n]), + .rx_sync (rx_sync[n]), + .rx_gt_rst (rx_gt_rst[n]), + .rx_gt_rst_m (rx_gt_rst_m[n]), + .rx_gt_charisk (rx_gt_charisk[((4*n)+3):(4*n)]), + .rx_gt_disperr (rx_gt_disperr[((4*n)+3):(4*n)]), + .rx_gt_notintable (rx_gt_notintable[((4*n)+3):(4*n)]), + .rx_gt_data (rx_gt_data[((32*n)+31):(32*n)]), + .rx_gt_comma_align_enb (rx_gt_comma_align_enb[n]), + .rx_gt_ilas_f (rx_gt_ilas_f[((4*n)+3):(4*n)]), + .rx_gt_ilas_q (rx_gt_ilas_q[((4*n)+3):(4*n)]), + .rx_gt_ilas_a (rx_gt_ilas_a[((4*n)+3):(4*n)]), + .rx_gt_ilas_r (rx_gt_ilas_r[((4*n)+3):(4*n)]), + .rx_gt_cgs_k (rx_gt_cgs_k[((4*n)+3):(4*n)]), + .rx_ip_rst (rx_ip_rst[n]), + .rx_ip_sof (rx_ip_sof[((4*n)+3):(4*n)]), + .rx_ip_data (rx_ip_data[((32*n)+31):(32*n)]), + .rx_ip_sysref (rx_ip_sysref[n]), + .rx_ip_sync (rx_ip_sync[n]), + .rx_ip_rst_done (rx_ip_rst_done[n]), + .rx_user_ready (rx_user_ready[n]), + .rx_rst_done_m (rx_rst_done_m[n]), + .rx_pll_locked_m (rx_pll_locked_m[n]), + .rx_user_ready_m (rx_user_ready_m[n]), + .rx_rst_done_in (rx_rst_done_shift[n]), + .rx_rst_done_out (rx_rst_done[n]), + .rx_pll_locked_in (rx_pll_locked_shift[n]), + .rx_pll_locked_out (rx_pll_locked[n]), + .tx_p (tx_p[n]), + .tx_n (tx_n[n]), .tx_out_clk (tx_out_clk[n]), - .tx_rst_done (tx_rst_done_s[n]), - .tx_pll_locked (tx_pll_locked_s[n]), - .tx_clk (tx_clk), - .tx_charisk (tx_gt_charisk_mux_s[n*4+3:n*4]), - .tx_data (tx_gt_data_mux_s[n*32+31:n*32]), + .tx_clk (tx_clk[n]), + .tx_rst (tx_rst[n]), + .tx_rst_m (tx_rst_m[n]), + .tx_data (tx_data[((32*n)+31):(32*n)]), + .tx_sysref (tx_sysref[n]), + .tx_sync (tx_sync[n]), + .tx_gt_rst (tx_gt_rst[n]), + .tx_gt_rst_m (tx_gt_rst_m[n]), + .tx_gt_charisk (tx_gt_charisk[((4*TX_DATA_SEL[n])+3):(4*TX_DATA_SEL[n])]), + .tx_gt_data (tx_gt_data[((32*TX_DATA_SEL[n])+31):(32*TX_DATA_SEL[n])]), + .tx_ip_rst (tx_ip_rst[n]), + .tx_ip_data (tx_ip_data[((32*n)+31):(32*n)]), + .tx_ip_sysref (tx_ip_sysref[n]), + .tx_ip_sync (tx_ip_sync[n]), + .tx_ip_rst_done (tx_ip_rst_done[n]), + .tx_user_ready (tx_user_ready[n]), + .tx_rst_done_m (tx_rst_done_m[n]), + .tx_pll_locked_m (tx_pll_locked_m[n]), + .tx_user_ready_m (tx_user_ready_m[n]), + .tx_rst_done_in (tx_rst_done_shift[n]), + .tx_rst_done_out (tx_rst_done[n]), + .tx_pll_locked_in (tx_pll_locked_shift[n]), + .tx_pll_locked_out (tx_pll_locked[n]), + .up_es_dma_req (up_es_dma_req[n]), + .up_es_dma_addr (up_es_dma_addr[((32*n)+31):(32*n)]), + .up_es_dma_data (up_es_dma_data[((32*n)+31):(32*n)]), + .up_es_dma_ack (up_es_dma_ack[n]), + .up_es_dma_err (up_es_dma_err[n]), + .up_rstn (up_rstn), .up_clk (up_clk), - .up_drp_sel (up_drp_sel_s), - .up_drp_addr (up_drp_addr_s), - .up_drp_wr (up_drp_wr_s), - .up_drp_wdata (up_drp_wdata_s), - .up_drp_rdata (up_drp_rdata_gt_s[n]), - .up_drp_ready (up_drp_ready_gt_s[n]), - .up_drp_lanesel (up_drp_lanesel_s), - .up_drp_rxrate (up_drp_rxrate_gt_s[n])); + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack[n]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata[((32*n)+31):(32*n)]), + .up_rack (up_rack[n])); end endgenerate - // eye scan - - ad_gt_es #(.GTH_GTX_N(PCORE_DEVICE_TYPE)) i_gt_es ( + ad_gt_common_1 #( + .ID (0), + .GTH_GTX_N (GTH_GTX_N), + .QPLL0_ENABLE (QPLL0_ENABLE), + .QPLL0_REFCLK_DIV (QPLL0_REFCLK_DIV), + .QPLL0_CFG (QPLL0_CFG), + .QPLL0_FBDIV_RATIO (QPLL0_FBDIV_RATIO), + .QPLL0_FBDIV (QPLL0_FBDIV), + .QPLL1_ENABLE (QPLL1_ENABLE), + .QPLL1_REFCLK_DIV (QPLL1_REFCLK_DIV), + .QPLL1_CFG (QPLL1_CFG), + .QPLL1_FBDIV_RATIO (QPLL1_FBDIV_RATIO), + .QPLL1_FBDIV (QPLL1_FBDIV)) + i_common ( + .qpll0_rst (qpll0_rst), + .qpll0_ref_clk_in (qpll0_ref_clk_in), + .qpll1_rst (qpll1_rst), + .qpll1_ref_clk_in (qpll1_ref_clk_in), + .qpll_clk (qpll_clk), + .qpll_ref_clk (qpll_ref_clk), + .qpll_locked (qpll_locked), .up_rstn (up_rstn), .up_clk (up_clk), - .up_es_drp_sel (up_es_drp_sel_s), - .up_es_drp_wr (up_es_drp_wr_s), - .up_es_drp_addr (up_es_drp_addr_s), - .up_es_drp_wdata (up_es_drp_wdata_s), - .up_es_drp_rdata (up_es_drp_rdata_s), - .up_es_drp_ready (up_es_drp_ready_s), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack[8]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata[((32*8)+31):(32*8)]), + .up_rack (up_rack[8])); + + ad_gt_es_axi i_es_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_dma_req_0 (up_es_dma_req[0]), + .up_es_dma_addr_0 (up_es_dma_addr[((32*0)+31):(32*0)]), + .up_es_dma_data_0 (up_es_dma_data[((32*0)+31):(32*0)]), + .up_es_dma_ack_0 (up_es_dma_ack[0]), + .up_es_dma_err_0 (up_es_dma_err[0]), + .up_es_dma_req_1 (up_es_dma_req[1]), + .up_es_dma_addr_1 (up_es_dma_addr[((32*1)+31):(32*1)]), + .up_es_dma_data_1 (up_es_dma_data[((32*1)+31):(32*1)]), + .up_es_dma_ack_1 (up_es_dma_ack[1]), + .up_es_dma_err_1 (up_es_dma_err[1]), + .up_es_dma_req_2 (up_es_dma_req[2]), + .up_es_dma_addr_2 (up_es_dma_addr[((32*2)+31):(32*2)]), + .up_es_dma_data_2 (up_es_dma_data[((32*2)+31):(32*2)]), + .up_es_dma_ack_2 (up_es_dma_ack[2]), + .up_es_dma_err_2 (up_es_dma_err[2]), + .up_es_dma_req_3 (up_es_dma_req[3]), + .up_es_dma_addr_3 (up_es_dma_addr[((32*3)+31):(32*3)]), + .up_es_dma_data_3 (up_es_dma_data[((32*3)+31):(32*3)]), + .up_es_dma_ack_3 (up_es_dma_ack[3]), + .up_es_dma_err_3 (up_es_dma_err[3]), + .up_es_dma_req_4 (up_es_dma_req[4]), + .up_es_dma_addr_4 (up_es_dma_addr[((32*4)+31):(32*4)]), + .up_es_dma_data_4 (up_es_dma_data[((32*4)+31):(32*4)]), + .up_es_dma_ack_4 (up_es_dma_ack[4]), + .up_es_dma_err_4 (up_es_dma_err[4]), + .up_es_dma_req_5 (up_es_dma_req[5]), + .up_es_dma_addr_5 (up_es_dma_addr[((32*5)+31):(32*5)]), + .up_es_dma_data_5 (up_es_dma_data[((32*5)+31):(32*5)]), + .up_es_dma_ack_5 (up_es_dma_ack[5]), + .up_es_dma_err_5 (up_es_dma_err[5]), + .up_es_dma_req_6 (up_es_dma_req[6]), + .up_es_dma_addr_6 (up_es_dma_addr[((32*6)+31):(32*6)]), + .up_es_dma_data_6 (up_es_dma_data[((32*6)+31):(32*6)]), + .up_es_dma_ack_6 (up_es_dma_ack[6]), + .up_es_dma_err_6 (up_es_dma_err[6]), + .up_es_dma_req_7 (up_es_dma_req[7]), + .up_es_dma_addr_7 (up_es_dma_addr[((32*7)+31):(32*7)]), + .up_es_dma_data_7 (up_es_dma_data[((32*7)+31):(32*7)]), + .up_es_dma_ack_7 (up_es_dma_ack[7]), + .up_es_dma_err_7 (up_es_dma_err[7]), .axi_awvalid (m_axi_awvalid), .axi_awaddr (m_axi_awaddr), .axi_awprot (m_axi_awprot), @@ -973,119 +1250,9 @@ module axi_jesd_gt ( .axi_arprot (m_axi_arprot), .axi_arready (m_axi_arready), .axi_rvalid (m_axi_rvalid), - .axi_rdata (m_axi_rdata), .axi_rresp (m_axi_rresp), - .axi_rready (m_axi_rready), - .up_lpm_dfe_n (up_lpm_dfe_n_s), - .up_es_start (up_es_start_s), - .up_es_stop (up_es_stop_s), - .up_es_init (up_es_init_s), - .up_es_sdata0 (up_es_sdata0_s), - .up_es_sdata1 (up_es_sdata1_s), - .up_es_sdata2 (up_es_sdata2_s), - .up_es_sdata3 (up_es_sdata3_s), - .up_es_sdata4 (up_es_sdata4_s), - .up_es_qdata0 (up_es_qdata0_s), - .up_es_qdata1 (up_es_qdata1_s), - .up_es_qdata2 (up_es_qdata2_s), - .up_es_qdata3 (up_es_qdata3_s), - .up_es_qdata4 (up_es_qdata4_s), - .up_es_prescale (up_es_prescale_s), - .up_es_hoffset_min (up_es_hoffset_min_s), - .up_es_hoffset_max (up_es_hoffset_max_s), - .up_es_hoffset_step (up_es_hoffset_step_s), - .up_es_voffset_min (up_es_voffset_min_s), - .up_es_voffset_max (up_es_voffset_max_s), - .up_es_voffset_step (up_es_voffset_step_s), - .up_es_voffset_range (up_es_voffset_range_s), - .up_es_start_addr (up_es_start_addr_s), - .up_es_dmaerr (up_es_dmaerr_s), - .up_es_status (up_es_status_s)); - - // processor - - up_gt #(.PCORE_ID(PCORE_ID), .PCORE_DEVICE_TYPE(PCORE_DEVICE_TYPE)) i_up_gt ( - .gt_pll_rst (gt_pll_rst), - .gt_rx_rst (gt_rx_rst), - .gt_tx_rst (gt_tx_rst), - .up_lpm_dfe_n (up_lpm_dfe_n_s), - .up_cpll_pd (up_cpll_pd_s), - .up_rx_sys_clk_sel (up_rx_sys_clk_sel_s), - .up_rx_out_clk_sel (up_rx_out_clk_sel_s), - .up_tx_sys_clk_sel (up_tx_sys_clk_sel_s), - .up_tx_out_clk_sel (up_tx_out_clk_sel_s), - .rx_clk (rx_clk), - .rx_rst (rx_rst), - .rx_jesd_rst (rx_jesd_rst), - .rx_ext_sysref (rx_ext_sysref), - .rx_sysref (rx_sysref), - .rx_ip_sync (rx_ip_sync), - .rx_sync (rx_sync), - .rx_rst_done (rx_rst_done_extn_s[7:0]), - .rx_pll_locked (rx_pll_locked_extn_s[7:0]), - .rx_error (1'd0), - .rx_rst_done_up (rx_rst_done), - .tx_clk (tx_clk), - .tx_rst (tx_rst), - .tx_jesd_rst (tx_jesd_rst), - .tx_ext_sysref (tx_ext_sysref), - .tx_sysref (tx_sysref), - .tx_sync (tx_sync), - .tx_ip_sync (tx_ip_sync), - .tx_rst_done (tx_rst_done_extn_s[7:0]), - .tx_pll_locked (tx_pll_locked_extn_s[7:0]), - .tx_error (1'd0), - .tx_rst_done_up (tx_rst_done), - .up_drp_sel (up_drp_sel_s), - .up_drp_wr (up_drp_wr_s), - .up_drp_addr (up_drp_addr_s), - .up_drp_wdata (up_drp_wdata_s), - .up_drp_rdata (up_drp_rdata_s), - .up_drp_ready (up_drp_ready_s), - .up_drp_lanesel (up_drp_lanesel_s), - .up_drp_rxrate (up_drp_rxrate_s), - .up_es_drp_sel (up_es_drp_sel_s), - .up_es_drp_wr (up_es_drp_wr_s), - .up_es_drp_addr (up_es_drp_addr_s), - .up_es_drp_wdata (up_es_drp_wdata_s), - .up_es_drp_rdata (up_es_drp_rdata_s), - .up_es_drp_ready (up_es_drp_ready_s), - .up_es_start (up_es_start_s), - .up_es_stop (up_es_stop_s), - .up_es_init (up_es_init_s), - .up_es_prescale (up_es_prescale_s), - .up_es_voffset_range (up_es_voffset_range_s), - .up_es_voffset_step (up_es_voffset_step_s), - .up_es_voffset_max (up_es_voffset_max_s), - .up_es_voffset_min (up_es_voffset_min_s), - .up_es_hoffset_max (up_es_hoffset_max_s), - .up_es_hoffset_min (up_es_hoffset_min_s), - .up_es_hoffset_step (up_es_hoffset_step_s), - .up_es_start_addr (up_es_start_addr_s), - .up_es_sdata0 (up_es_sdata0_s), - .up_es_sdata1 (up_es_sdata1_s), - .up_es_sdata2 (up_es_sdata2_s), - .up_es_sdata3 (up_es_sdata3_s), - .up_es_sdata4 (up_es_sdata4_s), - .up_es_qdata0 (up_es_qdata0_s), - .up_es_qdata1 (up_es_qdata1_s), - .up_es_qdata2 (up_es_qdata2_s), - .up_es_qdata3 (up_es_qdata3_s), - .up_es_qdata4 (up_es_qdata4_s), - .up_es_dmaerr (up_es_dmaerr_s), - .up_es_status (up_es_status_s), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s), - .up_rack (up_rack_s)); - - // axi interface + .axi_rdata (m_axi_rdata), + .axi_rready (m_axi_rready)); up_axi i_up_axi ( .up_rstn (up_rstn), @@ -1107,14 +1274,14 @@ module axi_jesd_gt ( .up_axi_rresp (s_axi_rresp), .up_axi_rdata (s_axi_rdata), .up_axi_rready (s_axi_rready), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s), - .up_rack (up_rack_s)); + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_d), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_d), + .up_rack (up_rack_d)); endmodule diff --git a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl b/library/axi_jesd_gt/axi_jesd_gt_ip.tcl index ba6c5a606..fb926fbfe 100644 --- a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl +++ b/library/axi_jesd_gt/axi_jesd_gt_ip.tcl @@ -5,15 +5,19 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_jesd_gt adi_ip_files axi_jesd_gt [list \ - "$ad_hdl_dir/library/common/ad_gt_common_1.v" \ - "$ad_hdl_dir/library/common/ad_gt_channel_1.v" \ - "$ad_hdl_dir/library/common/ad_gt_es.v" \ - "$ad_hdl_dir/library/common/ad_jesd_align.v" \ + "axi_jesd_gt_constr.xdc" \ "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/ad_gt_channel.v" \ + "$ad_hdl_dir/library/common/ad_gt_common.v" \ + "$ad_hdl_dir/library/common/ad_gt_es.v" \ + "$ad_hdl_dir/library/common/ad_gt_es_axi.v" \ + "$ad_hdl_dir/library/common/ad_gt_channel_1.v" \ + "$ad_hdl_dir/library/common/ad_gt_common_1.v" \ + "$ad_hdl_dir/library/common/ad_jesd_align.v" \ "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_gt_channel.v" \ "$ad_hdl_dir/library/common/up_gt.v" \ - "axi_jesd_gt.v" \ - "axi_jesd_gt_constr.xdc" ] + "axi_jesd_gt.v" ] adi_ip_properties axi_jesd_gt @@ -28,37 +32,37 @@ set_property value axi_aresetn [ipx::get_bus_parameters ASSOCIATED_RESET \ -of_objects [ipx::get_bus_interfaces axi_signal_clock \ -of_objects [ipx::current_core]]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.PCORE_NUM_OF_RX_LANES')) > 1} \ - [ipx::get_ports *rx_gt_*_1* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.PCORE_NUM_OF_RX_LANES')) > 2} \ - [ipx::get_ports *rx_gt_*_2* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.PCORE_NUM_OF_RX_LANES')) > 3} \ - [ipx::get_ports *rx_gt_*_3* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.PCORE_NUM_OF_RX_LANES')) > 4} \ - [ipx::get_ports *rx_gt_*_4* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.PCORE_NUM_OF_RX_LANES')) > 5} \ - [ipx::get_ports *rx_gt_*_5* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.PCORE_NUM_OF_RX_LANES')) > 6} \ - [ipx::get_ports *rx_gt_*_6* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.PCORE_NUM_OF_RX_LANES')) > 7} \ - [ipx::get_ports *rx_gt_*_7* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ + [ipx::get_ports *rx_*_1* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ + [ipx::get_ports *rx_*_2* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ + [ipx::get_ports *rx_*_3* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ + [ipx::get_ports *rx_*_4* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ + [ipx::get_ports *rx_*_5* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ + [ipx::get_ports *rx_*_6* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ + [ipx::get_ports *rx_*_7* -of_objects [ipx::current_core]] -set_property driver_value 0 [ipx::get_ports *tx_gt_charisk_* -of_objects [ipx::current_core]] -set_property driver_value 0 [ipx::get_ports *tx_gt_data_* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.PCORE_NUM_OF_TX_LANES')) > 1} \ - [ipx::get_ports *tx_gt_*_1* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.PCORE_NUM_OF_TX_LANES')) > 2} \ - [ipx::get_ports *tx_gt_*_2* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.PCORE_NUM_OF_TX_LANES')) > 3} \ - [ipx::get_ports *tx_gt_*_3* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.PCORE_NUM_OF_TX_LANES')) > 4} \ - [ipx::get_ports *tx_gt_*_4* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.PCORE_NUM_OF_TX_LANES')) > 5} \ - [ipx::get_ports *tx_gt_*_5* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.PCORE_NUM_OF_TX_LANES')) > 6} \ - [ipx::get_ports *tx_gt_*_6* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.PCORE_NUM_OF_TX_LANES')) > 7} \ - [ipx::get_ports *tx_gt_*_7* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \ + [ipx::get_ports *tx_*_1* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \ + [ipx::get_ports *tx_*_2* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \ + [ipx::get_ports *tx_*_3* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \ + [ipx::get_ports *tx_*_4* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \ + [ipx::get_ports *tx_*_5* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \ + [ipx::get_ports *tx_*_6* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \ + [ipx::get_ports *tx_*_7* -of_objects [ipx::current_core]] + +set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] ipx::save_core [ipx::current_core]