axi_adc_decimate: Re-implemented FIR filter
The minimum decimation rate of the CIC block is five, this means data arrives at the FIR filter at most every five clock cycles. The decimation rate of the filter is two so the filter produces an output at most every ten clock cycles. This allows for ten clock cycles to compute the result. The current implementation of the filter uses a fully pipelined architecture with one multiplier for each coefficient. Which then do work for one clock cycle and sit idle for the next nine clock cycles. Rework the filter to be sequential reducing the number of required multipliers to one. In addition exploit the symmetric structure of the filter to make use of the preadder reducing the required multiply operations by two. This significantly reduces the logic utilization of the filter as well as moderately reduces power consumption. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
Lars-Peter Clausen
parent
737418a1b0
commit
3e7325b29a
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@ -1,331 +1,281 @@
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// -------------------------------------------------------------
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2017(c) Analog Devices, Inc.
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//
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// Module: fir_decim
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// Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0.
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// Generated on: 2016-07-05 15:45:22
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// -------------------------------------------------------------
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// -------------------------------------------------------------
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// HDL Code Generation Options:
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// All rights reserved.
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//
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// FIRAdderStyle: tree
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// OptimizeForHDL: on
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// EDAScriptGeneration: off
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// AddPipelineRegisters: on
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// Name: fir_decim
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// TargetLanguage: Verilog
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// TestBenchName: fo_copy_tb
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// TestBenchStimulus: step ramp chirp noise
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// GenerateHDLTestBench: off
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// -------------------------------------------------------------
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// HDL Implementation : Fully parallel
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// Multipliers : 6
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// Folding Factor : 1
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// -------------------------------------------------------------
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// Filter Settings:
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// Discrete-Time FIR Multirate Filter (real)
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// -----------------------------------------
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// Filter Structure : Direct-Form FIR Polyphase Decimator
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// Decimation Factor : 2
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// Polyphase Length : 3
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// Filter Length : 6
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// Stable : Yes
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// Linear Phase : Yes (Type 2)
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// Arithmetic : fixed
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// Numerator : s12,11 -> [-1 1)
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// -------------------------------------------------------------
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1 ns / 1 ns
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module fir_decim
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(
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clk,
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clk_enable,
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reset,
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filter_in,
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filter_out,
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ce_out
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);
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module fir_decim #(
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parameter USE_DSP48E = 1
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) (
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input clk,
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input clk_enable,
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input reset,
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input signed [11:0] filter_in,
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output reg signed [25:0] filter_out,
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output reg ce_out
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);
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input clk;
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input clk_enable;
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input reset;
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input signed [11:0] filter_in; //sfix12_En11
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output signed [25:0] filter_out; //sfix26_En22
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output ce_out;
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localparam signed [11:0] coeffphase1_1 = 12'b000011010101; //sfix12_En11
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localparam signed [11:0] coeffphase1_2 = 12'b011011110010; //sfix12_En11
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localparam signed [11:0] coeffphase1_3 = 12'b110000111110; //sfix12_En11
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////////////////////////////////////////////////////////////////
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//Module Architecture: fir_decim
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////////////////////////////////////////////////////////////////
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// Local Functions
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// Type Definitions
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// Constants
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parameter signed [11:0] coeffphase1_1 = 12'b000011010101; //sfix12_En11
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parameter signed [11:0] coeffphase1_2 = 12'b011011110010; //sfix12_En11
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parameter signed [11:0] coeffphase1_3 = 12'b110000111110; //sfix12_En11
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parameter signed [11:0] coeffphase2_1 = 12'b110000111110; //sfix12_En11
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parameter signed [11:0] coeffphase2_2 = 12'b011011110010; //sfix12_En11
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parameter signed [11:0] coeffphase2_3 = 12'b000011010101; //sfix12_En11
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// We know that clk_enable is asserted at most every 5th clock cycle and the
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// output is decimated by two. So we have 10 clock cycles to compute the
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// result. That's plenty of time considering that there are only 6
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// coefficients.
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// Signals
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reg [1:0] ring_count; // ufix2
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wire phase_0; // boolean
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wire phase_1; // boolean
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reg ce_out_reg; // boolean
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reg signed [11:0] input_register; // sfix12_En11
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reg signed [11:0] input_pipeline_phase0 [0:1] ; // sfix12_En11
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reg signed [11:0] input_pipeline_phase1 [0:2] ; // sfix12_En11
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wire signed [23:0] product_phase0_1; // sfix24_En22
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wire signed [23:0] product_phase0_2; // sfix24_En22
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wire signed [23:0] product_phase0_3; // sfix24_En22
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wire signed [23:0] product_phase1_1; // sfix24_En22
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wire signed [23:0] product_phase1_2; // sfix24_En22
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wire signed [23:0] product_phase1_3; // sfix24_En22
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reg signed [23:0] product_pipeline_phase0_1; // sfix24_En22
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reg signed [23:0] product_pipeline_phase0_2; // sfix24_En22
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reg signed [23:0] product_pipeline_phase0_3; // sfix24_En22
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reg signed [23:0] product_pipeline_phase1_1; // sfix24_En22
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reg signed [23:0] product_pipeline_phase1_2; // sfix24_En22
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reg signed [23:0] product_pipeline_phase1_3; // sfix24_En22
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wire signed [25:0] sumvector1 [0:2] ; // sfix26_En22
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wire signed [23:0] add_signext; // sfix24_En22
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wire signed [23:0] add_signext_1; // sfix24_En22
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wire signed [24:0] add_temp; // sfix25_En22
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wire signed [23:0] add_signext_2; // sfix24_En22
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wire signed [23:0] add_signext_3; // sfix24_En22
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wire signed [24:0] add_temp_1; // sfix25_En22
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wire signed [23:0] add_signext_4; // sfix24_En22
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wire signed [23:0] add_signext_5; // sfix24_En22
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wire signed [24:0] add_temp_2; // sfix25_En22
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reg signed [25:0] sumdelay_pipeline1 [0:2] ; // sfix26_En22
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wire signed [25:0] sumvector2 [0:1] ; // sfix26_En22
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wire signed [25:0] add_signext_6; // sfix26_En22
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wire signed [25:0] add_signext_7; // sfix26_En22
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wire signed [26:0] add_temp_3; // sfix27_En22
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reg signed [25:0] sumdelay_pipeline2 [0:1] ; // sfix26_En22
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wire signed [25:0] sum3; // sfix26_En22
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wire signed [25:0] add_signext_8; // sfix26_En22
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wire signed [25:0] add_signext_9; // sfix26_En22
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wire signed [26:0] add_temp_4; // sfix27_En22
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reg ce_delayline1; // boolean
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reg ce_delayline2; // boolean
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reg ce_delayline3; // boolean
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reg ce_delayline4; // boolean
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reg ce_delayline5; // boolean
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reg ce_delayline6; // boolean
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reg ce_delayline7; // boolean
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reg ce_delayline8; // boolean
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wire ce_gated; // boolean
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reg signed [25:0] output_register; // sfix26_En22
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reg active = 1'b0;
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reg active_d1 = 1'b0;
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reg active_d2 = 1'b0;
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// Block Statements
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always @ (posedge clk or posedge reset)
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begin: ce_output
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if (reset == 1'b1) begin
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ring_count <= 1;
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reg [1:0] count = 2'b00;
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reg phase = 1'b1;
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reg ready = 1'b0;
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reg [3:0] storage0[0:11];
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reg [3:0] storage1[0:11];
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reg signed [11:0] data0;
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reg signed [11:0] data1;
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reg signed [11:0] coeff;
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wire signed [25:0] sum;
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integer j;
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initial begin
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for (j = 0; j < 12; j = j + 1) begin
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storage0[j] <= 'h00;
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storage1[j] <= 'h00;
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end
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end
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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phase <= 1'b1;
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end else begin
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if (clk_enable == 1'b1) begin
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phase <= phase + 1'b1;
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end
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else begin
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if (clk_enable == 1'b1) begin
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ring_count <= {ring_count[0], ring_count[1]};
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end
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end
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end // ce_output
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end
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end
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assign phase_0 = ring_count[0] && clk_enable;
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always @(posedge clk) begin
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if (clk_enable == 1'b1 && phase == 1'b1) begin
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active <= 1'b1;
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end else if (count == 'h2) begin
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active <= 1'b0;
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end
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active_d1 <= active;
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active_d2 <= active_d1;
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end
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assign phase_1 = ring_count[1] && clk_enable;
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always @(posedge clk) begin
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if (active == 1'b1) begin
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case (count)
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'h2: count <= 'h0;
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default: count <= count + 1'b1;
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endcase
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end
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end
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// ------------------ CE Output Register ------------------
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always @(posedge clk) begin
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if (active_d1 == 1'b0 && active_d2 == 1'b1) begin
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ready <= 1'b1;
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end else begin
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ready <= 1'b0;
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end
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end
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always @ (posedge clk or posedge reset)
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begin: ce_output_register
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if (reset == 1'b1) begin
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ce_out_reg <= 1'b0;
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end
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else begin
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ce_out_reg <= phase_1;
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end
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end // ce_output_register
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always @ (posedge clk or posedge reset)
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begin: input_reg_process
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if (reset == 1'b1) begin
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input_register <= 0;
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end
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else begin
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if (clk_enable == 1'b1) begin
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input_register <= filter_in;
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generate
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genvar i;
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for (i = 0; i < 12; i = i + 1) begin
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always @(posedge clk) begin
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if (clk_enable == 1'b1) begin
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if (phase == 1'b0) begin
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storage0[i] <= {storage0[i][2:0],filter_in[i]};
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end
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if (phase == 1'b1) begin
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storage1[i] <= {storage1[i][2:0],filter_in[i]};
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end
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end
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end // input_reg_process
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end
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always @( posedge clk or posedge reset)
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begin: Delay_Pipeline_Phase0_process
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if (reset == 1'b1) begin
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input_pipeline_phase0[0] <= 0;
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input_pipeline_phase0[1] <= 0;
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always @(*) begin
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data0[i] <= storage0[i][2-count];
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data1[i] <= storage1[i][count];
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end
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end
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endgenerate
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always @(*) begin
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case (count)
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'h0: coeff <= coeffphase1_1;
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'h1: coeff <= coeffphase1_2;
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'h2: coeff <= coeffphase1_3;
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default: coeff <= 'h00;
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endcase
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end
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generate if (USE_DSP48E) begin
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wire [47:0] _sum;
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wire [6:0] opmode = {1'b0,active_d2,5'b00101};
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// Can't exceed 26 bit.
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assign sum = _sum[43:18];
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// MAC with pre-adder
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DSP48E1 #(
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.ACASCREG (0),
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.ADREG (1),
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.ALUMODEREG (0),
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.AREG (0),
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.AUTORESET_PATDET ("NO_RESET"),
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.A_INPUT ("DIRECT"),
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.BCASCREG (1),
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.BREG (1),
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.B_INPUT ("DIRECT"),
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.CARRYINREG (0),
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.CARRYINSELREG (0),
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.CREG (0),
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.DREG (0),
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.INMODEREG (0),
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.MASK (48'h3fffffffffff),
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.MREG (1),
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.OPMODEREG (1),
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.PATTERN (48'h000000000000),
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.PREG (1),
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.SEL_MASK ("MASK"),
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.SEL_PATTERN ("PATTERN"),
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.USE_DPORT ("TRUE"),
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.USE_MULT ("MULTIPLY"),
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.USE_PATTERN_DETECT ("NO_PATDET"),
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.USE_SIMD ("ONE48"))
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i_dsp_mac (
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.CLK (clk),
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.A ({5'h0,data0[11],data0,12'h0}), // MSB aligned to 24-bit, 25th bit signed extended
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.B ({coeff,6'b0}),
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.C (48'h00),
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.D ({data1[11],data1,12'h0}),
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.MULTSIGNIN (1'b0),
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.CARRYIN (1'b0),
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.CARRYCASCIN (1'b0),
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.ACIN (30'h0),
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.BCIN (18'h0),
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.PCIN (48'h0),
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.P (_sum),
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.MULTSIGNOUT (),
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.CARRYOUT (),
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.CARRYCASCOUT (),
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.ACOUT (),
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.BCOUT (),
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.PCOUT (),
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.ALUMODE (4'b0000),
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.CARRYINSEL (3'h0),
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.INMODE (5'b00100),
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.OPMODE (opmode),
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.PATTERNBDETECT (),
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.PATTERNDETECT (),
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.OVERFLOW (),
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.UNDERFLOW (),
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.CEA1 (1'b0),
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.CEA2 (1'b0),
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.CEAD (active),
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.CEALUMODE (1'b0),
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.CEB1 (1'b0),
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.CEB2 (active),
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.CEC (1'b0),
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.CECARRYIN (1'b0),
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.CECTRL (active),
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.CED (1'b0),
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.CEINMODE (1'b0),
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.CEM (active_d1),
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.CEP (active_d2),
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.RSTA (1'b0),
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.RSTALLCARRYIN (1'b0),
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.RSTALUMODE (1'b0),
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.RSTB (1'b0),
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.RSTC (1'b0),
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.RSTCTRL (1'b0),
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.RSTD (1'b0),
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.RSTINMODE (1'b0),
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.RSTM (1'b0),
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.RSTP (1'b0)
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);
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end else begin
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reg signed [25:0] _sum = 'h00;
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reg signed [12:0] pre_adder;
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reg signed [11:0] coeff_d1;
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reg signed [23:0] product = 'h00;
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assign sum = _sum;
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always @(posedge clk) begin
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if (active == 1'b1) begin
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pre_adder <= data0 + data1;
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coeff_d1 <= coeff;
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end
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else begin
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if (phase_1 == 1'b1) begin
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input_pipeline_phase0[0] <= input_register;
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input_pipeline_phase0[1] <= input_pipeline_phase0[0];
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end
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if (active_d1 == 1'b1) begin
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product <= coeff_d1 * pre_adder;
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end
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end // Delay_Pipeline_Phase0_process
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always @( posedge clk or posedge reset)
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begin: Delay_Pipeline_Phase1_process
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if (reset == 1'b1) begin
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input_pipeline_phase1[0] <= 0;
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input_pipeline_phase1[1] <= 0;
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input_pipeline_phase1[2] <= 0;
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if (reset == 1'b1 || ready == 1'b1) begin
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_sum <= 'h00;
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end else if (active_d2 == 1'b1) begin
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_sum <= _sum + product;
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end
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else begin
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if (phase_0 == 1'b1) begin
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input_pipeline_phase1[0] <= input_register;
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input_pipeline_phase1[1] <= input_pipeline_phase1[0];
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input_pipeline_phase1[2] <= input_pipeline_phase1[1];
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end
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end
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end // Delay_Pipeline_Phase1_process
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end
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end
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||||
endgenerate
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
ce_out <= 1'b0;
|
||||
end else begin
|
||||
ce_out <= ready;
|
||||
end
|
||||
end
|
||||
|
||||
assign product_phase0_1 = input_register * coeffphase1_1;
|
||||
always @(posedge clk) begin
|
||||
if (ready == 1'b1) begin
|
||||
filter_out <= sum;
|
||||
end
|
||||
end
|
||||
|
||||
assign product_phase0_2 = input_pipeline_phase0[0] * coeffphase1_2;
|
||||
|
||||
assign product_phase0_3 = input_pipeline_phase0[1] * coeffphase1_3;
|
||||
|
||||
assign product_phase1_1 = input_pipeline_phase1[0] * coeffphase2_1;
|
||||
|
||||
assign product_phase1_2 = input_pipeline_phase1[1] * coeffphase2_2;
|
||||
|
||||
assign product_phase1_3 = input_pipeline_phase1[2] * coeffphase2_3;
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: product_pipeline_process1
|
||||
if (reset == 1'b1) begin
|
||||
product_pipeline_phase0_1 <= 0;
|
||||
product_pipeline_phase1_1 <= 0;
|
||||
product_pipeline_phase0_2 <= 0;
|
||||
product_pipeline_phase1_2 <= 0;
|
||||
product_pipeline_phase0_3 <= 0;
|
||||
product_pipeline_phase1_3 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
product_pipeline_phase0_1 <= product_phase0_1;
|
||||
product_pipeline_phase1_1 <= product_phase1_1;
|
||||
product_pipeline_phase0_2 <= product_phase0_2;
|
||||
product_pipeline_phase1_2 <= product_phase1_2;
|
||||
product_pipeline_phase0_3 <= product_phase0_3;
|
||||
product_pipeline_phase1_3 <= product_phase1_3;
|
||||
end
|
||||
end
|
||||
end // product_pipeline_process1
|
||||
|
||||
assign add_signext = product_pipeline_phase1_1;
|
||||
assign add_signext_1 = product_pipeline_phase1_2;
|
||||
assign add_temp = add_signext + add_signext_1;
|
||||
assign sumvector1[0] = $signed({{1{add_temp[24]}}, add_temp});
|
||||
|
||||
assign add_signext_2 = product_pipeline_phase1_3;
|
||||
assign add_signext_3 = product_pipeline_phase0_1;
|
||||
assign add_temp_1 = add_signext_2 + add_signext_3;
|
||||
assign sumvector1[1] = $signed({{1{add_temp_1[24]}}, add_temp_1});
|
||||
|
||||
assign add_signext_4 = product_pipeline_phase0_2;
|
||||
assign add_signext_5 = product_pipeline_phase0_3;
|
||||
assign add_temp_2 = add_signext_4 + add_signext_5;
|
||||
assign sumvector1[2] = $signed({{1{add_temp_2[24]}}, add_temp_2});
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: sumdelay_pipeline_process1
|
||||
if (reset == 1'b1) begin
|
||||
sumdelay_pipeline1[0] <= 0;
|
||||
sumdelay_pipeline1[1] <= 0;
|
||||
sumdelay_pipeline1[2] <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
sumdelay_pipeline1[0] <= sumvector1[0];
|
||||
sumdelay_pipeline1[1] <= sumvector1[1];
|
||||
sumdelay_pipeline1[2] <= sumvector1[2];
|
||||
end
|
||||
end
|
||||
end // sumdelay_pipeline_process1
|
||||
|
||||
assign add_signext_6 = sumdelay_pipeline1[0];
|
||||
assign add_signext_7 = sumdelay_pipeline1[1];
|
||||
assign add_temp_3 = add_signext_6 + add_signext_7;
|
||||
assign sumvector2[0] = add_temp_3[25:0];
|
||||
|
||||
assign sumvector2[1] = sumdelay_pipeline1[2];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: sumdelay_pipeline_process2
|
||||
if (reset == 1'b1) begin
|
||||
sumdelay_pipeline2[0] <= 0;
|
||||
sumdelay_pipeline2[1] <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
sumdelay_pipeline2[0] <= sumvector2[0];
|
||||
sumdelay_pipeline2[1] <= sumvector2[1];
|
||||
end
|
||||
end
|
||||
end // sumdelay_pipeline_process2
|
||||
|
||||
assign add_signext_8 = sumdelay_pipeline2[0];
|
||||
assign add_signext_9 = sumdelay_pipeline2[1];
|
||||
assign add_temp_4 = add_signext_8 + add_signext_9;
|
||||
assign sum3 = add_temp_4[25:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: ce_delay
|
||||
if (reset == 1'b1) begin
|
||||
ce_delayline1 <= 1'b0;
|
||||
ce_delayline2 <= 1'b0;
|
||||
ce_delayline3 <= 1'b0;
|
||||
ce_delayline4 <= 1'b0;
|
||||
ce_delayline5 <= 1'b0;
|
||||
ce_delayline6 <= 1'b0;
|
||||
ce_delayline7 <= 1'b0;
|
||||
ce_delayline8 <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
ce_delayline1 <= clk_enable;
|
||||
ce_delayline2 <= ce_delayline1;
|
||||
ce_delayline3 <= ce_delayline2;
|
||||
ce_delayline4 <= ce_delayline3;
|
||||
ce_delayline5 <= ce_delayline4;
|
||||
ce_delayline6 <= ce_delayline5;
|
||||
ce_delayline7 <= ce_delayline6;
|
||||
ce_delayline8 <= ce_delayline7;
|
||||
end
|
||||
end
|
||||
end // ce_delay
|
||||
|
||||
assign ce_gated = ce_delayline8 & ce_out_reg;
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: output_register_process
|
||||
if (reset == 1'b1) begin
|
||||
output_register <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
output_register <= sum3;
|
||||
end
|
||||
end
|
||||
end // output_register_process
|
||||
|
||||
// Assignment Statements
|
||||
assign ce_out = ce_gated;
|
||||
assign filter_out = output_register;
|
||||
endmodule // fir_decim
|
||||
endmodule
|
||||
|
|
|
|||
Loading…
Reference in New Issue